Embedian SMARC-iMX8M Series, User Manual, Page: 132 / 174

Embedian, Inc.
132
SMARC-iMX8M Computer on Module User’s Manual v.1.0
SMARC Edge Finger NXP i.MX8M CPU Type Description
Pin# Pin Name Ball Mode Signal Name
P121 I2C_PM_CK E7 ALT0 I2C1_SCL__
I2C1_SCL IO OD Power management
I2C bus clock
P122 I2C_PM_DAT E8 ALT0 I2C1_SDA__
I2C1_SDA IO OD Power management
I2C bus data
P123 BOOT_SEL0# P5 ALT0 GPIO1_IO04__
GPIO1_IO4 I SYSBOOT and Line
De‐multiplexer Logic
Pulled up on Module.
Driven by OD part on
Carrier.
P124 BOOT_SEL1# P7 ALT0 GPIO1_IO05__
GPIO1_IO5 I SYSBOOT and Line
De‐multiplexer Logic
Pulled up on Module.
Driven by OD part on
Carrier.
P125 BOOT_SEL2# N5 ALT0 GPIO1_IO06__
GPIO1_IO6 I SYSBOOT and Line
De‐multiplexer Logic
Pulled up on Module.
Driven by OD part on
Carrier.
P126 RESET_OUT# O General purpose
reset output to
Carrier board.