Embedian, Inc.
24
SMARC-iMX8M Computer on Module User’s Manual v.1.0
2.1.6 LVDS Interface
The
SMARC‐iMX8M
implements two 18 / 24 bit single channel LVDS output
streams that are defined in SMARC 2.0 edge connector for the Primary
displays from
i.MX8M MIPI_DSI
interface. They can also be configured as an
18 / 24 bit dual‐channel LVDS directly out of the
SMARC
Module.
The
LVDS
LCD
signals found on the
SMARC‐i.MX8M
offers two LVDS channels,
with resolutions up to 1,920 × 1,200 @60 fps at 24 bpp. They are generated
from
MIPI_DSI
signals from the
NXP
®
i.MX8M
Cortex A53 processor passing
through a TI
SN65DSI84 MIPI® DSI
Bridge To FLATLINK™ LVDS. Each channel
consists of one clock pair and four data pairs. The
LVDS
signals support the
flow of
MIPI DSI
data from the
i.MX8M
CPU to external display devices
through LVDS interface.
The LVDS ports support the following configurations:
One single channel output
One dual channel output: single input split to two output channels
Note:
1. The I2C slave address of
SN65DSI84
is 0x2C.
2. The
LVDS
interface can be used either as a single channel or as a dual
channel. The default LVDS configuration is 24‐bit single channel LVDS. To
change this configuration, user need to change 0x18 register bit [2:4].
Please refer to
Embedian
u‐boot BSP official release for details.