EMI Design Issues
The high-speed digital signals associated with microcontroller designs can generate
unintentional electromagnetic interference (EMI). High-speed voltage transitions
generate RF currents that can radiate from a product if a nearby length of wire or
piece of metal acts as an antenna.
Products that use a PLT-22 transceiver together with a Neuron Chip will generally
need to demonstrate compliance with EMI limits enforced by various regulatory
agencies. In the USA, the FCC
6
requires that unintentional radiators comply with
Part 15 level “A” for industrial products, and level “B” for consumer and household
products. Most European countries require compliance to CENELEC EN 50065-1.
Similar regulations are imposed in most countries throughout the world.
In addition to the following discussion, designers of PLT-22 transceiver-based nodes
are strongly encouraged to read reference [11] for a good treatment of EMC. The
EDN Designer's Guide to EMC
12
is also a good source of design advice regarding
EMC issues.
Designing Systems for EMC (Electromagnetic Compatibility)
Careful PCB layout is important to ensure that a PLT-22 transceiver-based node will
achieve the desired level of EMC. A typical PLT-22 transceiver-based node will have
several digital signals switching in the 1MHz-10MHz range. These signals will
generate both voltage noise near the signal traces, and current noise in the signal
and power supply traces. The goal of good node design is to keep voltage and current
noise from coupling out of the product enclosure.
It is very important to minimize the “leakage” capacitance from circuit traces in the
node to any external metal near the node because this capacitance provides a path
for the digital noise to couple out of the product enclosure. Figure 6.1 shows the
leakage capacitances to earth ground from a node's logic ground (C
leak,GND
) and
from a digital signal line in the node (C
leak,SIGNAL
). If the PLT-22 transceiver-
based node is housed inside a metal chassis, then that metal chassis will probably
have the largest leakage capacitance to other nearby pieces of metal. If the node is
housed inside a plastic package, then PCB ground guarding must be used to
minimize C
leak,SIGNAL
. Effective guarding of digital traces with logic ground
reduces C
leak,SIGNAL
significantly, which in turn reduces the level of common-mode
RF currents driven onto the AC mains.
When a node is mounted near a piece of metal, especially metal that is earth
grounded, any leakage capacitance from fast signal lines to that metal will provide a
path for RF currents to flow. When V
gate
is pulled down to logic ground, the voltage
of logic ground with respect to earth ground will increase slightly. When V
gate
pulls
up to V
DD5
, logic ground will be pushed down slightly with respect to earth ground.
As C
leak,SIGNAL
increases, a larger current flows during V
gate
transitions,
generating more common-mode RF current. This common-mode RF current can
generate EMI in the 30MHz-300MHz frequency band, thereby exceeding
FCC/CENELEC levels, even when C
leak,SIGNAL
from a clock line to earth ground is
less than 1pF. This means that it is essential to guard the clock lines.
6-2
Design and Test for Electromagnetic Compatibility
Summary of Contents for LONWORKS PLT-22
Page 6: ...iv Echelon...
Page 14: ...1 8 Introduction...
Page 67: ...LONWORKS PLT 22 Transceiver s User Guide 5 7 Figure 5 3 Capacitor Input Power Supply Schematic...
Page 92: ...6 10 Design and Test for Electromagnetic Compatibility...
Page 110: ...7 18 Communication Performance Verification...
Page 114: ...8 4 References...
Page 118: ...A 4 Appendix A...
