Echelon LONWORKS PLT-22, User Manual

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the ground traces and V
DD5
trace between the PLT-22 transceiver and the Neuron
Chip should have impedances as low as possible.
The PLT-22 transceiver's CKOUT pin provides a clock suitable for driving the
Neuron Chip CLK1 at 1.25MHz, 2.5MHz, 5MHz, or 10MHz. The frequency of the
CKOUT pin (Neuron Chip CLK1 input) is selected by two pins, CKSEL0 and
CKSEL1/TXON, as shown in table 2.4. The Neuron Chip CLK2 pin is not connected.
The length of the CKOUT line should be kept to an absolute minimum and should in
no case exceed 50mm (2").
Table 2.4 PLT-22 Transceiver Output Clock Frequency Settings
CKSEL1/TXON CKSEL0 CKOUT FREQ. (MHz)
≥ 4.7k to GND (or open) GND 1.25
≥ 4.7k to GND (or open) V
DD
2.5
4.7k to V
DD
V
DD
5
4.7k to V
DD
GND 10
!
The CKSEL1/TXON pin must never be connected directly to a supply rail. The
CKSEL1/TXON pin will draw large currents and potentially damage the
PLT-22 transceiver if it is connected directly to a supply rail. The CKSEL0
pin may be tied directly to V
DD5
or GND.
Note that when the PLT-22 transceiver is operated in its new dual
frequency mode (as described in Chapter 3, PLT-22 Transceiver
Programming ) the Neuron Chip clock must be set to be 2.5MHz or higher.
The PLT-22 transceiver ~RESET pin is designed to connect directly to the Neuron
Chip ~RESET pin. The
Neuron Chip Data Book
2,3,18
provides information on the
Neuron Chip’s external reset circuitry. Depending on the particular Neuron
Chip version used, a Low Voltage Indicator (LVI) circuit such as the
Motorola MC33064 or Dallas 1233 may be necessary to supply a reset signal
to both the Neuron Chip and the PLT-22 transceiver. All of the application
circuits shown in this documentation include an LVI chip. Consult your Neuron
Chip manufacturer for the latest reset circuit requirements. Whether an LVI chip or
a simpler discrete circuit is required, the ~RESET pin of the PLT-22 should always
be tied directly to the ~RESET pin of the Neuron Chip. To minimize the effect of
ESD discharges on the Neuron Chip ~RESET pin, use two external 56pF ceramic
capacitors, one tied between ~RESET and V
DD5
, the other between ~RESET and
GND. The capacitors should be placed as close as possible to the Neuron
Chip ~RESET pin. Note that the PLT-22 transceiver already incorporates two
56pF capacitors on the ~RESET line internal to the transceiver. These internal
capacitors should be taken into account when calculating the total allowable
capacitive load on the Neuron Chip ~RESET pin, as specified in the Neuron Chip
Data Book
2,3,18
.
L
ON
W
ORKS
PLT-22 Transceiver User’s Guide 2-9