DTK Apex 386/33, User Manual

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Cache Coherency — Hardware Transparency
Write-Back eliminates stale data in the main memory caused by a
cache-write operation. However, if a cache is used in a system in which
more than one device has access to the main memory (a multi-
processing system or a DMA system, for example), another stale data
problem is introduced.
If new data is written to main memory by one device, the cache
maintained by another device will contain stale data. A system that
prevents the stale cache data problem is said to maintain cache
coherency. The PEM-3301 uses the method of hardware transparency
to maintain cache coherency.
Hardware ensures cache coherency by allowing all accesses to
memory mapped by a cache to be seen by the cache. This is ac-
complished by routing the accesses of the all devices to the memory
through the same cache.
The following figures show the cache memory organization and cache
memory system implementation of the your mainboard.
Chapter 6: Appendix 27