I/O Address
Map
The I/O address map of your mainboard is given below. Note that the
I/O addresses from hex 000 to hex OFF are reserved for the mainboard,
and the addresses from hex 100 to hex 3FF are available
on the AT I/O
bus.
Address Range
000-01 F
020-03F
040-05F
060-06F
070-07F
080-09F
0A0-0BF
0C0-0DF
0F0
0F1
0F&0FF
1 F0-1F8
200-207
278-27F
2F8-2FF
300-31 F
360-36F
378-37F
380-38F
3A0-3AF
3B0-3BF
3C0-3CF
3D0-3DF
3F0-3F7
3F8-3FF
Device
DMA Controller 1, 8237
Master Interrupt Controller, 8259
Timer, 8254
Keyboard Controller, 8042
Real-time clock, NMI mask
DMA Page Register,74LS612
Interrupt Controller2, 8259
DMA Controller 2, 8237
Clear Math Coprocessor Busy
Reset Math Coprocessor
Math Coprocessor
Fixed Disk
Game I/O
Parallel Printer Port 2
Serial Port 2
Prototype Card
Reserved
Parallel Printer Port 1
SDLC, bisynchronous 2
Bisynchronous 1
Monochrome Display and Printer Adapter
Enhanced Graphics Display Adapter
Color Graphics Monitor Adapter
Diskette Controller
Serial Port 1
Table 6-11: I/0 Address Map
Chapter 6: Appendix
41
Summary of Contents for Apex 386/33
Page 1: ...K E E N 3 3 0 4 33MHz 386 SYSTEM User s Manual...
Page 16: ......
Page 31: ...Table 1 7 Power Cord Specifications Chapter 1 System Overview 15...
Page 39: ...Chapter 2 Setting Up Your System...
Page 42: ...Figure 2 1 PEM 3301 Motherboard Layout Chapter 2 Setting Up Your System 3...
Page 51: ...Figure 2 7 Cache Configurations 12 Chapter 2 Setting Up Your System...
Page 52: ......
Page 55: ...Figure 2 12 8MB Total Onboard memory 16 Chapter 2 Setting Up Your System...
Page 62: ...Figure 2 17 PEM 3300 Motherboard Layout Chapter 2 Setting Up Your System 23...
Page 71: ...Figure 2 23 Cache Configurations 64KB cache 256KB cache 32 Chapter 2 Setting Up Your System...
Page 72: ...Table 2 12 DRAM Configurations Chapter 2 Setting Up Your System 33...
Page 83: ......
Page 84: ......
Page 100: ...Chapter 4 Keyboard...
Page 110: ...Troubleshooting...
Page 119: ......
Page 133: ......
Page 134: ......
Page 135: ...I...
Page 136: ......
Page 137: ......
Page 138: ......
Page 144: ...Figure 6 14 Direct Mapped Cache Organization Chapter 6 Appendix 25...
Page 147: ...Figure 6 15 Cache Architecture 28 Chapter 6 Appendix...
Page 151: ...Interrupt Controllers Table 6 9 Interrupt Controllers 32 Chapter 6 Appendix...
Page 163: ...Figure 6 19 Pin Assignments of the 32 bit Memory Expansion Bus 44 Chapter 6 Appendix...
Page 164: ......