DTK Apex 386/33, User Manual

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System Timers
There are three programmable timer/counters in the 8254 portion of
the VLSI 82C100 chip. The three independent 18-bit counters and six
software-programmable counter modes connect to system software
They appear as an array of four external I/O ports. Three ports are
used as counters, and the fourth is a control registerfor mode program-
ming. The timer channels are defined as channels 0, 1 and 2.
They are used as follows:
Channel 0
Gate 0
CLK IN 0
CLK OUT 0
System Timer
Always enabled
1.190MHz clock
Interrupt Controller, 8259 IRQ0
Channel 1
Refresh Request Generator
Gate 1
CLK IN 1
Always enabled
1.19 0
CLK OUT 1
MHz clock
Refresh Request Cycle
Channel 2
Gate 2
CLK IN 2
CLK OUT 2
Speaker Tone Generator
Controlled by
bit0 of I/O port hex 61
1.190MHz clock
Audio frequency output to speaker
System Interrupts
The CPU may be interrupted by two 8259 Interrupt Controllers in the
VLSI 82Cl00 as well as the NMI signal. This allows 16 levels of
interrupt, each with its own level of priority. Any interrupt including NMI
can be disabled. The following table shows the interrupt level assign-
ments.
Level
NMI Function
Mainboard memory parity or I/O
channel check
Chapter 6: Appendix
31