Table 3–29 (Cont.) I/O ROM-Based Diagnostic Descriptions
Group
Test
Subtest
Description
G: 0
T: 1
I/O VIC Test
G: 0
T: 1
S: 0
VIC Register Test
G: 0
T: 1
S: 1
VIC Interrupt Test
G: 0
T: 2
I/O Firewall Test
G: 0
T: 2
S: 0
Firewall Register Test
G: 0
T: 2
S: 1
Firewall Rail Master Test
G: 0
T: 2
S: 2
Firewall Cross Check Error Test
G: 0
T: 3
I/O Cache Test
G: 0
T: 3
S: 0
CACHE Control Register Bit Test
G: 0
T: 3
S: 1
CACHE Minimum Bank Test
G: 0
T: 3
S: 2
CACHE Data Integrity Test
G: 0
T: 3
S: 3
CACHE Tag Integrity Test
G: 0
T: 3
S: 4
CACHE Tag Parity Detection Test
G: 0
T: 3
S: 5
CACHE Tag Parity Generation Test
G: 0
T: 3
S: 6
CACHE Data Parity Checking Test
G: 0
T: 4
I/O NVRAM Test
G: 0
T: 4
S: 0
Module Data EEPROM Integrity Test
G: 0
T: 4
S: 1
Module I2C EEPROM Integrity Test
G: 0
T: 5
I/O RAM Test
G: 0
T: 5
S: 0
SOC RAM Test
G: 1
I/O Eself Pcard Test
G: 1
T: 0
I/O SLIM Test
G: 1
T: 0
S: 0
SLIM Register Test
G: 1
T: 0
S: 1
SLIM RAM Test
G: 1
T: 1
I/O SWIFT Test
G: 1
T: 1
S: 0
SWIFT Reset Test
G: 1
T: 1
S: 1
SWIFT Register Test
G: 1
T: 1
S: 2
SWIFT Interrupt Test
G: 1
T: 1
S: 3
SWIFT Internal Loopback Test
G: 1
T: 2
I/O LANCE Test
G: 1
T: 2
S: 0
LANCE Register Test
G: 1
T: 2
S: 1
LANCE Internal Loopback Test
G: 1
T: 2
S: 2
LANCE Interrupt Test
System Maintenance 3–35