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Figure 4–15 SubDCB Links to DCB
Zone A DCB Offset
Zone B DCB Offset
Number of Entries
DCB Entry 1
DCB Entry n
Number of Entries
DCB Entry 1
DCB Entry 2
DCB Entry n−1
DCB Entry n
CCA
Zone A DCB
SubDCB for DCB Entry 1
Number of Entries
DCB Entry 1
DCB Entry 2
DCB Entry n−1
DCB Entry n
SubDCB for DCB Entry n
DCB Base
+ Offset
DCB Base
+ Offset
CCA Base
+ Offset
MR−0020−93RAGS
4.8.2.2 CPU Module SubDCB
The CPU SubDCB is used to represent the memory modules (MMBs) available on
the CPU module. Table 4–38 describes the CPU SubDCB components. Table 4–39
describes the CPU SubDCB entry components.
4–64 Error Handling and Analysis