Table 4–19 System Register Entry Descriptions
Entry
Content
Offset
SYSFLT
JXD System Fault Register
0
SYSADR
JXD System Error Address Register
4
DMAADR
DMA Error Address Register
8
DMA_IO_ADDR
DMA Engine I/O Error Address Register
12
JCSR_A
JXD Control and Status Register - Zone A
16
JCSR_B
JXD Control and Status Register - Zone B
20
JDIAG_P_A
JXD Diagnostic Error Register - Zone A, primary rail
24
JDIAG_M_A
JXD Diagnostic Error Register - Zone A, mirror rail
28
JDIAG_P_B
JXD Diagnostic Error Register - Zone B, primary rail
32
JDIAG_M_B
JXD Diagnostic Error Register - Zone B, mirror rail
36
ATMERR0_A
JXD ROM BUS ATM Error Register - Zone A
40
ATMERR0_B
JXD ROM BUS ATM Error Register - Zone B
44
DMASTS_A
DMA Status Register - Zone A
48
DMASTS_B
DMA Status Register - Zone B
52
MMBERR0_A
JXD ROM BUS MMB Error Register 0 - Zone A
56
MMBERR0_B
JXD ROM BUS MMB Error Register 0 - Zone B
60
MMBERR1_A
JXD ROM BUS MMB Error Register 1 - Zone A
64
MMBERR1_B
JXD ROM BUS MMB Error Register 1 - Zone B
68
SERCRS_A
Serial Cross-Link Control and Status Register - Zone A
72
SERCRS_B
Serial Cross-Link Control and Status Register - Zone B
76
SERMODE_A
Serial Cross-Link Mode Register - Zone A
80
SERMODE_B
Serial Cross-Link Mode Register - Zone B
84
BIU_ADDR_A
CPU BIU Address Register - Zone A
88
BIU_ADDR_B
CPU BIU Address Register - Zone B
92
BIU_STAT_A
CPU Fill Syndrome - Zone A
96
BIU_STAT_B
CPU Fill Syndrome - Zone B
100
BIU_CTL_A
CPU Fill Address - Zone A
104
BIU_CTL_B
CPU Fill Address - Zone B
108
4.4.5.2 End Actions
End action data is provided after diagnostics have completed running on a zone
or CPU which was removed from service as a result of a system error. It is
composed of console and diagnostic status and the contents of registers from the
failed zone/CPU at the time the original system error occurred. Table 4–20 lists
each register entry and its offset from the start of the data block.
4–28 Error Handling and Analysis