Table 3–28 (Cont.) CPU ROM-Based Diagnostic Descriptions
Group
Test
Subtest
Description
G: 0
T: 7
S: 5
DMA Sub-Trasfer Length Test
G: 0
T: 7
S: 6
DMA I/O Byte Alignment Test
G: 0
T: 7
S: 7
DMA Memory Byte Alignment Test
G: 0
T: 7
S: 8
DMA Maximum Transfer Length Test
G: 0
T: 8
XLINK Test
G: 0
T: 8
S: 0
XLINK Serial Cross-link Internal Loopback Test - Part 1
G: 0
T: 8
S: 1
XLINK Serial Cross-link Internal Loopback Request Test
G: 0
T: 8
S: 2
XLINK Serial Cross-link Internal Loopback Reply Test
G: 0
T: 8
S: 3
XLINK Serial Cross-link Internal Loopback Query Test
G: 0
T: 8
S: 4
XLINK Serial Cross-link External Loopback Test
G: 0
T: 8
S: 5
XLINK Serial Cross-link Communication Register Test
G: 0
T: 9
RESET Test
G: 0
T: 9
RESET CPU Module Hard Reset Test
G: 1
Zone Test
G: 1
T: 0
ACCESS Test
G: 1
T: 0
S: 0
ACCESS Parallel Xlink Loopback Test
G: 1
T: 0
S: 1
ACCESS I/O Module PATH ACCESS Test
G: 1
T: 0
S: 2
ACCESS I/O Module SSC Console Uart Test
G: 1
T: 1
DMA Test
G: 1
T: 2
INTERRUPT Test
G: 1
T: 3
ERROR Test
G: 1
T: 3
S: 0
ERROR I/O Crosscheck Test
G: 1
T: 4
RESET Test
G: 1
T: 4
S: 0
RESET CPU Module Zone Reset Test
G: 1
T: 4
S: 1
RESET I/O Module Reset Test
G: 2
System Test
G: 2
T: 0
Cross-link Mode Test
G: 2
T: 0
S: 0
Zone A (MASTER -> RESYNC MASTER -> DUPLEX)
Mode Test
G: 2
T: 0
S: 1
Zone B (MASTER -> RESYNC MASTER -> DUPLEX)
Mode Test
G: 2
T: 1
Zone A MASTER - Zone B SLAVE Mode Test
G: 2
T: 1
S: 0
ACCESS I/O Module Path Access Test
G: 2
T: 1
S: 1
ACCESS I/O Module SSC Console Uart Test
G: 2
T: 1
S: 2
ERROR I/O Crosscheck Test
G: 2
T: 2
Zone A RESYNC_MASTER - Zone B RESYNC_SLAVE
Mode Test
(continued on next page)
System Maintenance 3–33