Hercules III User Manual Rev A.2
www.diamondsystems.com
Page
65
Page 3 Register Definitions
Page Select and Reset Command: Base+0 (Write)
Bit:
7
6
5
4
3
2
1
0
Name:
HOLDOFF RESET
-
-
-
-
PAGE
HOLDOFF When this bit is set, the chip ignores any data written to this register. This bit enables
shadowing this register with another device at the same address.
RESET Reset the entire data acquisition circuit. After a reset, the following conditions are true:
1.
Digital I/O ports are set to input mode and all output registers are cleared to 0.
2.
A/D channel registers and range settings are cleared to zero, except for the Analog
Configuration Register (Base+1) which is set to 0x04.
3.
D/A channels are cleared to mid-scale or zero-scale, depending on the board jumper
setting.
4.
Counter/timers are disabled and counter registers are cleared to zero.
5.
Watchdog timer is disabled and timer registers are cleared to zero.
6.
FIFO is reset, causing all contents to be lost, and threshold is set to 1024 samples.
7.
The internal channel / gain table is reset to all zeros.
PAGE
Select page.
0 = Main features page
1 = Extended features page
2 = ID page
3 = Copyright notice page
Copyright Notice: Base+1 to Base+31 (Read)
Bit:
7
6
5
4
3
2
1
0
Name:
Copyright Notice Text
Copyright
Notice
Text
31 bytes of 8-bit ASCII-formatted copyright notice text.