Hercules III User Manual Rev A.2
www.diamondsystems.com
Page
48
I/O Register Definitions
Page 0 Register Definitions
Page Select and Reset Command: Base+0 (Write)
Bit:
7
6
5
4
3
2
1
0
Name:
HOLDOFF RESET
-
-
-
-
PAGE
HOLDOFF
When this bit is set, the chip ignores any data written to this register. This bit enables
shadowing this register with another device at the same address.
RESET
Reset the entire data acquisition circuit. After a reset, the following conditions are true:
1.
Digital I/O ports are set to input mode and all output registers are cleared to 0.
2.
A/D channel registers and range settings are cleared to zero, except for the Analog
Configuration Register (Base+1) which is set to 0x04.
3.
D/A channels are cleared to mid-scale or zero-scale, depending on the board jumper
setting.
4.
Counter/timers are disabled and counter registers are cleared to zero.
5.
Watchdog timer is disabled and timer registers are cleared to zero.
6.
FIFO is reset, causing all contents to be lost, and threshold is set to 1024 samples.
7.
The internal channel / gain table is reset to all zeros.
PAGE
Select page.
0 = Main features page
1 = Extended features page
2 = ID page
3 = Copyright notice page
A/D LSB: Base+0 (Read)
Bit:
7
6
5
4
3
2
1
0
Name:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD7-AD0 A/D LSB data. The A/D data must be read LSB first, followed by MSB.
Analog Configuration: Base+1 (Write)
Bit:
7
6
5
4
3
2
1
0
Name:
-
-
-
-
-
DABU
SEDIFF
ADBU
DABU
D/A output range: 0 = bipolar, 1 = unipolar. (Default on reset is unipolar mode).
SEDIFF A/D mode: 0 = single-ended, 1 = differential.
ADBU
A/D input range: 0 = bipolar, 1 = unipolar.