Hercules III User Manual Rev A.2
www.diamondsystems.com
Page
50
A/D Range/Status Readback: Base+4 (Read)
Bit:
7
6
5
4
3
2
1
0
Name:
ADBUSY
WAIT
DABUSY
DABU
SEDIFF
ADBU
G(1/0)
ADBUSY 0 = A/D is idle and data may be read out.
1 = A/D is performing an A/D conversion.
WAIT
0 = A/D circuit is ready to perform an A/D conversion.
1 = A/D circuit is settling on a new channel or gain setting. The program must not initiate an
A/D conversion while WAIT = 1.
DABUSY 0 = D/A circuit is idle / D/A output is stable.
1 = D/A circuit is transferring data to the D/A chip after writing data to the board.
DABU
0 = bipolar.
1 = unipolar D/A output range.
SEDIFF 0 = single-ended.
1 = differential A/D mode.
ADBU
0 = bipolar.
1 = unipolar A/D input range.
G(1/0)
Readback of global A/D gain setting. The individual A/D gain settings may not be read back.
D/A Channel: Base+5 (Write)
Bit:
7
6
5
4
3
2
1
0
Name:
SU
-
-
-
-
-
DACH(1/0)
SU
Simultaneous Update:
0 = Transparent (written directly to the DAC’s)/Simultaneous write.
1 = Latch and hold data (
DAC output not updated until “0” is written later).
DACH(1/0) D/A channel number.
Note: Writing to this register updates the selected D/A channel with the data currently stored in
registers Base+6 and Base+7. The high-order bit determines if the data is transferred directly out
to the DAC’s (transparent mode) or is latched and held for a later simultaneous update.
D/A LSB: Base+6 (Write)
Bit:
7
6
5
4
3
2
1
0
Name:
DA7-DA0
DA7-DA0 D/A LSB data.