Hercules III User Manual Rev A.2
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Page
57
Note: Counter/timer 0 is 24 bits wide and uses all three of the following registers. Counter/timer 1 is 16
bits wide and uses only registers 24 and 25. The bytes may be written and read in any order.
Counter/Timer Data Byte 1: Base+24 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
CTRD7-0
CTRD7-0 LSB for counter/timers 0 and 1.
Counter/Timer Data Byte 2: Base+25 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
CTRD15-8
CTRD15-8 CSB (middle byte) for counter/timer 0, MSB for counter/timer 1.
Counter/Timer Data Byte 3: Base+26 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
CTRD23-16
CTRD23-16 MSB for counter/timer 0.
Counter/Timer Control: Base+27 (Write)
Bit:
7
6
5
4
3
2
1
0
Name:
CTR
LATCH
GTDIS
GTEN
CTDIS
CTEN
LOAD
CLEAR
CTR
Counter number, 0 or 1.
LATCDH
Latch selected counter’s current data into bytes 1-3 or 1-2, as appropriate.
GTDIS
Disable gating on selected counter.
GTEN
Enable gating on selected counter.
CTDIS
Disable counting on selected counter.
CTEN
Enable counting on selected counter.
LOAD
Load selected counter with data in bytes 1-3 or 1-2, as appropriate.
CLEAR Clear selected counter to zero.