Hercules III User Manual Rev A.2
www.diamondsystems.com
Page
41
12. DATA ACQUISITION CIRCUIT
Hercules III contains a data acquisition subsystem consisting of digital I/O (DIO), watchdog timer (WDC),
counter/timer, pulse width modulation (PWM), and optional analog I/O features. The features of a board that
includes data acquisition are equivalent to a complete PC/104 add-on data acquisition module.
The A/D section includes a 16-bit A/D converter, 32 input channels and a 2048-sample (4kByte) FIFO. Input
ranges are programmable, and the maximum sampling rate is 250 KHz. The D/A section includes four 12-bit D/A
channels. The digital I/O section includes 40 lines with programmable direction. The counter/timer section
includes a 24-bit counter/timer to control A/D sampling rates and a 16-bit counter/timer for user applications. A 4-
channel PWM controller provides a way to automatically generate PWM-based waveforms.
High-speed A/D sampling is supported with interrupts and a FIFO. The FIFO is used to store a user-selected
number of samples, and an interrupt is generated when the FIFO reaches this threshold. Once the interrupt
occurs, an interrupt service routine reads the data from the FIFO. In this way, the interrupt rate is reduced by a
factor equal to the size of the FIFO threshold, enabling a faster A/D sampling rate. In DOS, or similar low-
overhead OSs, the circuit can operate at sampling rates of up to 250 KHz.
The interrupt rate, when using high sample-rates, is kept low because of the large FIFO buffer. With a 250 kHz
sampling rate and a FIFO threshold of 1024 samples (half-full), the interrupt rate is kept to a reasonable range of
approximately 250Hz. Reducing the FIFO interrupt threshold increases the interrupt rate for a given sampling
frequency, while increasing the threshold (especially the FIFO full threshold) increases the risk that samples may
be lost because of interrupt latency. The interrupt rate is an issue under multitasking OSs, such as Windows,
since interrupt handler latency can significant. For example, operating a serial port at maximum speed
(115kbaud) can tax the resources of a system's latency periods, especially when such activity is talking place over
the ISA bus, which is the case with both the serial ports and with the A/D FIFO. An interrupt rate of greater than
10 KHz can be difficult to sustain in Windows without losing samples.
The A/D circuit uses the default settings of I/O address range 0x240
– 0x25F (base address 0x240) and IRQ 5.
The IRQ setting can be changed if needed using jumper J4.
The figure on the following page shows a block diagram of the data acquisition circuit.