Hercules III User Manual Rev A.2
www.diamondsystems.com
Page
58
Watchdog Timer A LSB Data: Base+28 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
WDA7-0
WDA7-0 LSB of timer A divisor. Loading occurs for both bytes when the MSB is written.
Watchdog Timer A MSB Data: Base+29 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
WDA15-8
WDA15-8 MSB of timer A divisor. Loading occurs for both bytes when the MSB is written.
Watchdog Timer B Data: Base+30 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
WDB7-0
WDB7-0 Watchdog timer B data register. Loading occurs immediately upon writing to this register.
Watchdog Timer Configuration: Base+31 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
WDTRIG
-
WDEN
WDSMI
WDRST
WDT-1
WDEDGE
WDIEN
WDTRIG If this bit is set (1), the remaining bits of this register are ignored and, instead, watchdog timer
A is retriggered; i.e. reloaded with its initial value. If this bit is reset (0), the remaining bits in
this register are used to configure the watchdog timer circuit.
WDEN
Enable watchdog timer circuit:
0 = disabled
1 = enabled
WDSMI Enable SMI interrupt upon watchdog timer timeout.
WDRST Enable system reset upon watchdog timer timeout (setting this clears WDSMI).
WDT-1 Enable output pulse from timer A 1 clock early on WDO pin of I/O connectors. This allows
WDO to be connected to WDI to prevent watchdog timer timeout as long as the timer is
running.
WDEDGE Select active edge for hardware (external) retrigger:
0 = rising edge.
1 = falling edge.
WDIEN Enable external input hardware watchdog trigger instead of on-board software trigger.
0 = internal trigger only.
1 = external trigger plus internal trigger are enabled.