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Hercules III User Manual Rev A.2

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6. CONNECTORS

This section describes the on-board Hercules III connectors.

Note:

All cables mentioned in this chapter are included in Diamond Systems’ cable kit C-HRCE-KIT.

Some cables are also available individually.

6.1

PC/104 ISA Bus (J1, J2)

Connectors J1 and J2 carry the ISA bus signals. The following diagram shows the PC/104 A and B pin layout for
J1 and the C and D pin layout for J2.

IOCHCHK-

Ground

SD7

RESETDRV

SBHE-

MEMCS16--

SD6

+5V

LA23

IOCS16-

SD5

IRQ9

LA22

IRQ10

SD4

-5V

LA21

IRQ11

SD3

DRQ2

LA20

IRQ12

SD2

-12V

LA19

IRQ15

SD1

ENDXFR-

LA18

IRQ14

SD0

+12V

LA17

DACK0-

IOCHRDY

A10

B10

Key

MEMR-

DRQ0

AEN

A11

B11

SMEMW-

MEMW-

C10

D10

DACK5-

SA19

A12

B12

SMEMR-

SD8

C11

D11

DRQ5

SA18

A13

B13

IOW-

SD9

C12

D12

DACK6-

SA17

A14

B14

IOR-

SD10

C13

D13

DRQ6

SA16

A15

B15

DACK3-

SD11

C14

D14

DACK7-

SA15

A16

B16

DRQ3

SD12

C15

D15

DRQ7

SA14

A17

B17

DACK1-

SD13

C16

D16

SA13

A18

B18

DRQ1

SD14

C17

D17

MASTER-

SA12

A19

B19

REFRESH-

SD15

C18

D18

Ground

SA11

A20

B20

SYSCLK

Key

C19

D19

Ground

SA10

A21

B21

IRQ7

SA9

A22

B22

IRQ6

SA8

A23

B23

IRQ5

SA7

A24

B24

IRQ4

SA6

A25

B25

IRQ3

SA5

A26

B26

DACK2-

SA4

A27

B27

SA3

A28

B28

BALE

SA2

A29

B29

+5V

SA1

A30

B30

OSC

SA0

A31

B31

Ground

A32

B32

Ground

Summary of Contents for Hercules III

Page 1: ...Comment A 0 7 5 13 Initial version A 1 4 3 15 Minor updates A 2 5 9 18 Update Manufacturer PN for J35 Copyright 2015 2018 FOR TECHNICAL SUPPORT Diamond Systems Corporation PLEASE CONTACT 158 Commerci...

Page 2: ...ge Devices 11 3 2 6 Connecting Power 11 3 2 7 Display 11 3 3 BOOTING THE SYSTEM 12 3 3 1 BIOS Setup 12 3 3 2 Operating System Drivers 12 4 FUNCTIONAL OVERVIEW 13 4 1 FUNCTIONAL BLOCK DIAGRAM 13 4 2 FU...

Page 3: ...DRESS SELECTION JP7 32 7 5 PCI 104 CONNECTOR VIO JP9 33 7 6 COM3 COM4 CONFIGURATION JP10 JP11 33 8 SYSTEM OPERATION 34 8 1 SYSTEM RESOURCES 34 8 2 CONSOLE REDIRECTION TO A SERIAL PORT 34 8 3 WATCHDOG...

Page 4: ...sion Formulas for Bipolar Output Ranges 74 17 GENERATING AN ANALOG OUTPUT 75 17 1 COMPUTE THE D A CODE FOR THE DESIRED OUTPUT VOLTAGE 75 17 2 WRITE THE VALUE TO THE SELECTED OUTPUT CHANNEL REGISTERS 7...

Page 5: ...he edge to avoid possible shorting from this type of damage However these design rules are not sufficient to prevent damage in all situations A third cause of failure is when a metal screwdriver tip s...

Page 6: ...e acceptable range of voltages connected to digital I O signals is 0 5V and they can withstand about 0 5V beyond that 0 5 to 5 5V before being damaged However logic signals at 12V and even 24V are com...

Page 7: ...1600A 1G 1 6GHz 1GB Yes Standard model HRCE1600D 1G 1 6GHz 1GB DIO only MOQ of 50 HRCE1600A 2G 1 6GHz 2GB Yes MOQ of 50 HRCE1600D 2G 1 6GHz 2GB DIO only MOQ of 50 The Hercules III SBC brings the ISA a...

Page 8: ...s Watchdog timer 1 24 bit and 1 16 bit counter timer for A D sample rate control event counting and programmable interrupts Auto calibration with Universal Driver software support 2 3 Expansion Option...

Page 9: ...ules III User Manual covers basic hardware setup power connection system boot up and initial software configuration After Hercules III is up and running refer to the later sections of this manual for...

Page 10: ...cess to most of Hercules III s I O features The kit s cable assemblies are identified in the following table Number Quantity Cable No Description Connects to 1 1 6981006 Power out cable J15 2 1 698101...

Page 11: ...nto the appropriate connectors on the Main I O cable in the Hercules III Cable Kit cable number 6981022 Connect the end of the cable into connector J16 on Hercules III 3 2 4 mSATA Flashdisk Socket Her...

Page 12: ...meters Options configurable via Setup typically include Number and type of mass storage devices Boot device priority default is mSATA Video display type and resolution USB SATA serial and parallel int...

Page 13: ...Hercules III User Manual Rev A 2 www diamondsystems com Page 13 4 FUNCTIONAL OVERVIEW 4 1 Functional Block Diagram...

Page 14: ...h integrated agnetic The Wake On LAN feature requires integration with the board s power supply and Hercules III BIOS 4 2 4 USB Hercules III offers 5 user accessible USB 2 0 ports All ports have minim...

Page 15: ...tack through connectors press fit onto the board enabling expansion both above and below the board 4 2 12 Power Supply Hercules III contains an on board DC DC power supply with 55 watts of output powe...

Page 16: ...upported by the video chipset Console display and keyboard redirection to serial port DSC configurable default settings in battery less configurations Initialize USB keyboard mouse Customizable splash...

Page 17: ...Ports 1 2 3 4 J20 External Battery J21 USB 0 1 J22 USB 2 3 J23 USB 4 USB Device J24 LVDS LCD J25 VGA J27 Serial Ports 5 6 J28 LCD backlight power J32 CANbus J29 Power Input J34 GPS PPS J35 mSATA Sock...

Page 18: ...C3 D3 IRQ10 SD4 A5 B5 5V LA21 C4 D4 IRQ11 SD3 A6 B6 DRQ2 LA20 C5 D5 IRQ12 SD2 A7 B7 12V LA19 C6 D6 IRQ15 SD1 A8 B8 ENDXFR LA18 C7 D7 IRQ14 SD0 A9 B9 12V LA17 C8 D8 DACK0 IOCHRDY A10 B10 Key MEMR C9 D9...

Page 19: ...AD13 GND AD12 8 3 3V C BE1 AD15 3 3V 9 SERR GND SB0 PAR 10 GND PERR 3 3V SDONE 11 STOP 3 3V LOCK GND 12 3 3V TRDY GND DEVSEL 13 FRAME GND IRDY 3 3V 14 GND AD16 3 3V C BE2 15 AD18 3 3V AD17 GND 16 AD2...

Page 20: ...Output 5V In 17 18 N C N C 19 20 Ground Connector type Shrouded 1 dual row straight pin header with gold flash plating 6 5 Digital I O J8 Hercules III includes a 50 pin header J8 for all digital I O D...

Page 21: ...O port D programmable direction DIO E7 E0 Digital I O port E programmable direction E3 E0 may be configured for PWM signals EXTTRIG External A D trigger input TOUT0 1 Counter Timer 0 1 output PWM0 3...

Page 22: ...Vin 22 Vin 6 19 20 Vin 6 Vin 7 21 22 Vin 23 Vin 7 21 22 Vin 7 Vin 8 23 24 Vin 24 Vin 8 23 24 Vin 8 Vin 9 25 26 Vin 25 Vin 9 25 26 Vin 9 Vin 10 27 28 Vin 26 Vin 10 27 28 Vin 10 Vin 11 29 30 Vin 27 Vin...

Page 23: ...tor Tyco 1 640456 0 or equivalent Diamond Systems cable number 6981025 mates with this header 6 9 Audio AMP J13 Speaker Left 1 2 Volume Low Speaker Left 3 4 Volume Mid Wipe Line level Mono output 5 6...

Page 24: ...DTR 3 27 28 RI 3 NC 27 28 NC RXD 3 27 28 NC GND 29 30 NC GND 29 30 NC GND 29 30 NC Port 4 DCD 4 31 32 DSR 4 NC 31 32 NC NC 31 32 NC RXD 4 33 34 RTS 4 TXD RXD 4 33 34 TXD RXD 4 TXD 4 33 34 TXD 4 TXD 4...

Page 25: ...n a panel mount housing Connector type Standard 2 54mm dual row straight pin header with 4mm posts and gold flash plating 6 14 LCD Panel LVDS Interface J24 Connector J24 provides access to the interna...

Page 26: ...CD display only powered up when LCD display is active Ground Power Ground 0V Connector on board JST model number BM30B SRDS G TF or equivalent Mating cable connector JST model number SHDR 30V S B or e...

Page 27: ...10 NC Port 6 NC 11 12 NC RXD 6 13 14 RTS 6 TXD 6 15 16 CTS 6 NC 17 18 NC GND 19 20 NC Diamond Systems cable number C DB9M 2 provides a standard DB9 connector at each end and mates with this header 6...

Page 28: ...ocket Molex P N510210400 or equivalent Diamond Systems cable number 6981314 mates with this header 6 19 Power Input J29 Input power for Hercules III is supplied from a 7 40V external supply through co...

Page 29: ...mSATA modules Signal Name Pin Pin Signal Name NC 1 2 3 3V NC 3 4 GND NC 5 6 NC NC 7 8 NC GND 9 10 NC NC 11 12 NC NC 13 14 NC GND 15 16 NC Key NC 17 18 GND NC 19 20 NC GND 21 22 NC TX 23 24 3 3V TX 25...

Page 30: ...0 UIM_DATA 11 REFCLK 12 UIM_CLK 13 REFCLK 14 UIM_RESET 15 GND 16 UIM_VPP Mechanical Key 17 Reserved UIM_C8 18 GND 19 Reserved UIM_C4 20 W_DISABLE 21 GND 22 PERST 23 PERn0 24 3 3Vaux 25 PERp0 26 GND 27...

Page 31: ...ing table The default is no jumpers installed Pins Jumper installed Default 1 2 Provides 120 termination between the D D lines in RS 485 mode for COM3 No jumper 3 4 Provides 120 termination between th...

Page 32: ...ins Jumper installed Default 1 2 5V LCD backlight power Jumper 2 3 12V LCD backlight power No jumper JP6 LCD panel scan direction and frame rate control Pins Jumper installed Jumper not installed Defa...

Page 33: ...power No jumper 2 3 3 3V PCI VIO power Jumper 7 6 COM3 COM4 Configuration JP10 JP11 COM3 and COM4 can be configured as follows using jumpers JP10 and JP11 respectively The jumper settings work the sam...

Page 34: ...nfiguration are on board Ethernet sound video USB and any PC 104 Plus cards that are in the system These settings may also vary depending on what other devices are present in the system For example ad...

Page 35: ...tom for Continue C R after POST select Off default to turn off after POST or select On to remain on always 8 Exit the BIOS and save your settings 8 3 Watchdog Timer Hercules III contains a watchdog ti...

Page 36: ...nd COM2 may be modified COM1 and COM2 address and interrupt settings are configured using the Advanced Advanced Chipset Control I O Chip Device Configuration menu The addresses and IRQ selections of C...

Page 37: ...e aware that increasing these timings may adversely affect system stability with external add on PC 104 cards This setting has no direct affect on PCI or memory speeds it only affects ISA PC 104 devic...

Page 38: ...ion Direct default or Modem Console Type PC ANSI default VT100 VT100 8 bit PC ANSI 7 bit VT100 or VT UTF8 Flow Control CTS RTS default XON XOFF None Number of video Pages to support 1 default to 8 Not...

Page 39: ...base address and interrupt level The addresses of COM3 and COM4 are fixed The IRQ settings for COM3 and COM4 are fixed 10 3 USB Ports Four USB 2 0 ports USB0 through USB3 are accessible using cable a...

Page 40: ...ions included on the CD to install drivers for the different operating systems 11 1 2 BIOS Setting for Windows When using any version of Windows the Operating System selection in the BIOS setup menus...

Page 41: ...rrupt rate is reduced by a factor equal to the size of the FIFO threshold enabling a faster A D sampling rate In DOS or similar low overhead OSs the circuit can operate at sampling rates of up to 250...

Page 42: ...Hercules III User Manual Rev A 2 www diamondsystems com Page 42 Figure 1 Data Acquisition Block Diagram...

Page 43: ...Analog configuration register A D MSB 2 A D low channel A D low channel readback 3 A D high channel A D high channel readback 4 A D range register A D range status readback 5 D A channel 6 D A LSB 7 D...

Page 44: ...ROM Access Key Register FPGA Revision Code Page 2 Base Write Function Read Function 24 D A waveform future Feature ID register A D 25 D A waveform future Feature ID register D A 26 D A waveform future...

Page 45: ...N SCANEN CLKSEL CLKEN 14 15 FIFORST DARST CLRT CLRD CLRA ADSTART 16 DIOA7 DIOA6 DIOA5 DIOA4 DIOA3 DIOA2 DIOA1 DIOA0 17 DIOB7 DIOB6 DIOB5 DIOB4 DIOB3 DIOB2 DIOB1 DIOB0 18 DIOC7 DIOC6 DIOC5 DIOC4 DIOC3...

Page 46: ...OB7 DIOB6 DIOB5 DIOB4 DIOB3 DIOB2 DIOB1 DIOB0 18 DIOC7 DIOC6 DIOC5 DIOC4 DIOC3 DIOC2 DIOC1 DIOC0 19 DIOD7 DIOD6 DIOD5 DIOD4 DIOD3 DIOD2 DIOD1 DIOD0 20 DIOE7 DIOE6 DIOE5 DIOE4 DIOE3 DIOE2 DIOE1 DIOE0 2...

Page 47: ...9 A6 A5 A4 A3 A2 A1 A0 30 0 TDBUSE EEBUSY CMUXEN 0 0 0 0 31 Page 2 Write Offsets base 24 through base 31 are reserved for a future D A waveform generator circuit Base 7 6 5 4 3 2 1 0 0 HOLDOFF RESET P...

Page 48: ...t to 0x04 3 D A channels are cleared to mid scale or zero scale depending on the board jumper setting 4 Counter timers are disabled and counter registers are cleared to zero 5 Watchdog timer is disabl...

Page 49: ...well as a 32x4 table for all 32 input channels that can be used for individual input ranges for each channel The chip uses either the global input range setting or the individual range table based on...

Page 50: ...tput range SEDIFF 0 single ended 1 differential A D mode ADBU 0 bipolar 1 unipolar A D input range G 1 0 Readback of global A D gain setting The individual A D gain settings may not be read back D A C...

Page 51: ...threshold value MSB When the FIFO depth is greater than or equal to the FIFO threshold TF threshold flag 1 and an A D interrupt request will be generated if FIFOEN 1 and ADINTE 1 The FIFO size is 2048...

Page 52: ...LED Active high a simple status bit used to drive external LED Default is high upon power up SINGLE Indicates whether to use the global A D input range or the individual input range table for A D con...

Page 53: ...s programmed threshold set with FT11 0 When FIFOEN 0 and AINTE 1 A D interrupts occur according to the following conditions a if SCANEN 1 the interrupt occurs at the end of the scan and the FIFO conta...

Page 54: ...flag 0 FIFO is not full 1 FIFO is full TF FIFO threshold flag 0 FIFO depth is below the programmed threshold 1 FIFO depth is at or above the programmed threshold EF FIFO empty flag 0 not empty 1 empty...

Page 55: ...ration The current default value is 11 ADCH4 0 Current A D channel This is the channel sampled on the next A D conversion Digital I O Port A Base 16 Read Write Bit 7 6 5 4 3 2 1 0 Name DIOA7 0 DIOA7 0...

Page 56: ...E3 0 pins of I O connectors 1 PWM signals appear on DIOE3 0 pins of I O connectors See register Base 12 Configuration Register for details Digital I O Configuration Bit Programming Base 22 Write Bit 7...

Page 57: ...8 CSB middle byte for counter timer 0 MSB for counter timer 1 Counter Timer Data Byte 3 Base 26 Read Write Bit 7 6 5 4 3 2 1 0 Name CTRD23 16 CTRD23 16 MSB for counter timer 0 Counter Timer Control B...

Page 58: ...is bit is set 1 the remaining bits of this register are ignored and instead watchdog timer A is retriggered i e reloaded with its initial value If this bit is reset 0 the remaining bits in this regist...

Page 59: ...ge settings are cleared to zero except for the Analog Configuration Register Base 1 which is set to 0x04 3 D A channels are cleared to mid scale or zero scale depending on the board jumper setting 4 C...

Page 60: ...0 value of bits 1 3 are zero which is the load counter command If FLAG 1 selects internal clock source for both PWM counters 0 10MHz 1 100 KHz POL If FLAG 0 value of bits 1 3 are zero which is the loa...

Page 61: ...Base 30 Write Bit 7 6 5 4 3 2 1 0 Name EE_EN EE_RW RUNCAL CMUXEN TDACEN EE_EN EEPROM Enable Setting this bit initiates a transfer to from the EEPROM the direction is indicated by the EE_RW bit However...

Page 62: ...tus 0 disabled 1 enabled Note When either TDBUSY or EEBUSY is set do not access the data and address registers at Base 12 and Base 13 EEPROM Access Key Base 31 Write Bit 7 6 5 4 3 2 1 0 Name EEPROM Ac...

Page 63: ...eared to mid scale or zero scale depending on the board jumper setting 4 Counter timers are disabled and counter registers are cleared to zero 5 Watchdog timer is disabled and timer registers are clea...

Page 64: ...es the number of counter timers available on the board Chip ID LSB Base 28 Read Bit 7 6 5 4 3 2 1 0 Name ID7 0 ID7 0 See Chip ID MSB Base 29 below Chip ID MSB Base 29 Read Bit 7 6 5 4 3 2 1 0 Name ID1...

Page 65: ...d range settings are cleared to zero except for the Analog Configuration Register Base 1 which is set to 0x04 3 D A channels are cleared to mid scale or zero scale depending on the board jumper settin...

Page 66: ...or the inputs which causes them to be amplified before they reach the A D converter The gain setting is controlled in software which allows it to be changed on a channel by channel basis In general yo...

Page 67: ...o base 2 The first conversion is on channel 0 the second will be on channel 1 and the third will be on channel 2 The channel counter wraps around to the beginning so the fourth conversion will be on c...

Page 68: ...ther registers on the board the A D data may only be read one time because each time a byte is read from the FIFO the internal FIFO pointer advances and that byte is no longer available Reading data f...

Page 69: ...olic Formula Input Voltage for 5V Range 32768 VFS 5 0000V 32767 VFS 1 LSB 4 9998V 1 1 LSB 0 00015V 0 0 0 0000V 1 1 LSB 0 00015V 32767 VFS 1 LSB 4 9998V 14 8 2 Conversion Formula for Unipolar Input Ran...

Page 70: ...to an integral number of scans For example if the scan size is 8 channels the FIFO threshold should be set to 8 16 24 32 40 or 48 but not less than 8 This way the interrupt will occur at the end of t...

Page 71: ...d with ADCLK Base 4 bit 4 STS stays high during the entire scan multiple A D conversions A D interrupt occurs when the FIFO reaches its programmed threshold The interrupt routine reads the number of s...

Page 72: ...f this LSB is calculated as follows 1 LSB Output voltage range 4096 Example For Output range 0 10V Output voltage range 10V 0V 10V Therefore 1 LSB 10V 4096 2 44mV Example For Output range 10V Output v...

Page 73: ...unipolar mode 0 10V and Full scale range 10V 0V 10V if Desired output voltage 2 000V D A code 2 000V 10V 4096 819 2 819 Note the output code is always an integer For the unipolar output range 0 10V 1...

Page 74: ...l scale range 10V 10V 20V if Desired output voltage 2 000V D A code 2V 10V 2048 2048 2457 6 2458 For the bipolar output range 10V 1 LSB 1 4096 20V or 4 88mV The following table illustrates the relatio...

Page 75: ...ompute the LSB and MSB values LSB D A Code 255 keep only the low 8 bits MSB int D A code 256 strip off low 8 bits keep 4 high bits Example For Output code 1776 Compute LSB 1776 255 240 0xF0 and MSB in...

Page 76: ...with 16 bit accuracy exhibit gain and offset errors that vary depending on the gain setting The settings that work best for one range may not be sufficient to calibrate another If a circuit is calibra...

Page 77: ...OC4 DIOC3 DIOC2 DIOC1 DIOC0 19 DIOD7 DIOD6 DIOD5 DIOD4 DIOD3 DIOD2 DIOD1 DIOD0 20 DIOE7 DIOE6 DIOE5 DIOE4 DIOE3 DIOE2 DIOE1 DIOE0 21 22 MODE P2 P1 PO DIRE B2 DIRD B1 DIRC B0 DIRB D DIRA The digital I...

Page 78: ...except that it is a 16 bit counter Counter 1 also has an input a gate and an output These signals may be user provided on the I O header when DIOCTR is 0 or the input may come from the on board clock...

Page 79: ...le outp base 13 high outp base 14 high 15 Load the counter Counter 0 Counter 1 outp base 15 0x02 outp base 15 0x82 16 Enable the gate if desired The gating may be enabled or disabled at any time When...

Page 80: ...eared after stopping disabling and reading the counter If you clear a counter while it is enabled it continues to count incoming pulses so the counter value may not remain at zero 21 Stop disable the...

Page 81: ...les III watchdog timer is supported in the DSC Universal Driver software version 5 7 and later 21 1 Watchdog Timer Register Details The registers in the following table are used to program the watchdo...

Page 82: ...0 WDEDGE 0 Falling edge on WDI retriggers watchdog timer when WDIEN 1 1 Rising edge on WDI retriggers watchdog timer when WDIEN 1 I O Address 0x25F Read Write Bit 7 6 5 4 3 2 1 0 Name COM4EN COM3EN FP...

Page 83: ...mples programmable interrupt threshold 22 2 Analog Outputs data acquisition units only No of outputs 4 D A resolution 12 bits 1 4096 of full scale Output ranges Unipolar 0 10V or user programmable Bip...

Page 84: ...contain from 8GB to 64GB of solid state non volatile memory that operates like a disk drive without requiring additional driver software support The flashdisk module installs directly on the mSATA fl...

Page 85: ...PS 2 Audio HD audio with Realtek ALC262 CODEC Expansion sockets PCIe MiniCard full sized socket GPS receiver socket 24 2 Data Acquisition Circuitry Analog inputs 32 single ended 16 differential user...

Page 86: ...4V min 5 0V max Output current Logic 0 64mA max per line Logic 1 15mA max per line A D Pacer clock 24 bit down counter source 10MHz 1MHz or external signal General purpose 16 bit down counter source...

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Summary of Contents for Hercules III

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Diamond Systems Hercules III, User Manual, Page: 18 / 86

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Summary of Contents for Hercules III

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