DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 92 of 242
Field
Description of fields within Register file: 0x0F – System Event Status Register
HSRBP
reg:0F:00
bit:30
Host Side Receive Buffer Pointer. This is status flag relating to the operation of the receiver in
double-buffered mode. Section
describes this operation in detail.
Essentially HSRBP is an index indicating which of the buffer pairs the host side is accessing
(reading from currently or awaiting to read from when filled by the IC), while ICRBP is an index
indicating which of the buffer pairs the IC is accessing (writing to currently or will write to as
soon as a frame data arrives). The HSRBP bit is a READ ONLY status bit, its state is changed by
issuing the HRBPT command in
Register file: 0x0D – System Control Register
ICRBP
reg:0F:00
bit:31
IC side Receive Buffer Pointer. This is status flag relating to the operation of the receiver in
double-buffered mode. Section
describes this operation in detail.
Essentially ICRBP is an index indicating which of the buffer pairs the IC is accessing (writing to
currently or will write to as soon as a frame data arrives). The ICRBP bit is a READ ONLY status
bit.
RXRSCS
reg:0F:04
bit:0
Receiver Reed-Solomon Correction Status. This status bit indicates that the Reed-Solomon has
corrected at least one error in the frame being received. This is a low-level event status flag.
The RXRSCS bit probably not of interest to the host system. It was used during the verification
of the Reed-Solomon implementation. The RXRSCS bit cannot be used as an interrupt source.
The RXRSCS status bit can be cleared explicitly by writing a 1 to it. It is also automatically
cleared by the next receiver enable, including those caused by the RXAUTR auto-re-enable.
RXPREJ
reg:0F:04
bit:1
Receiver Preamble Rejection. This is a low-level event status flag, which is probably not of
interest to the host system. It was used during the IC implementation as part of tuning the
preamble detection algorithm. In the DW1000, preamble detection a two stage process
where preamble is initially seen and then has to be confirmed as continuing for a number of
symbols before the RXSFDD event status bit actually gets set. If the preamble is not confirmed
then the RXSFDD event status bit will not be set, but instead this RXPREJ status will be set. The
RXPREJ bit cannot be used as an interrupt source. The RXPREJ event status bit can be cleared
explicitly by writing a 1 to it. It is also automatically cleared by the next receiver enable,
including those caused by the RXAUTR auto-re-enable.
TXPUTE
reg:0F:04
bit:2
Transmit power up time error. This is a low-level event status flag. It applies when delayed
transmission is being used. Frame transmission will continue if this condition is detected, and
the RMARKER will be sent at the correct time, but that the initial few preamble symbols may
not transmit correctly. This may have a performance effect when a short preamble sequence
is being employed. The TXPUTE event status flag is READ ONLY. It will clear as soon as the
DW1000 begins to send preamble, (or if the DW1000 is returned to idle). Since the TX power-
up time is only a few symbol times in duration and because the TXPUTE bit clears at the start of
preamble, it is unlikely that the host system will see the TXPUTE bit set. The condition
therefore should be detected using the event counted in
Sub-Register 0x2F:1A – Transmitter
, (when counting is enabled by the EVC_EN bit in
0x2F:00 – Event Counter Control
The delayed transmit and receive functionality is described in detail in sections
and
–
reg:0F:04
bits:7–3
These bits are reserved
