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decaWave DW1000, User Manual

The decaWave DW1000 is an advanced wireless communication module that enables accurate and reliable ranging and positioning in a variety of applications. Enhance your experience with this cutting-edge technology by easily accessing the comprehensive user manual, available for free download at manualshive.com. Get the most out of your DW1000 with our detailed manual.

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DW1000 User Manual  

 

 

© Decawave Ltd 2017 

Version 2.12

 

Page 84 of 242 

 

 

Field 

Description of fields within Register file: 0x0E – System Event Mask Register 

MRXPHD

 

 
reg:0E:00 

bit:11

 

Mask receiver PHY header detect event.  When MRXPHD is 0 the RXPHD event status bit will 
not generate an interrupt.  When MRXPHD is 1 and the RXPHD event status bit is 1, the 
hardware IRQ interrupt line will be asserted to generate an interrupt. 

MRXPHE

 

 
reg:0E:00 

bit:12

 

Mask receiver PHY header error event.  When MRXPHE is 0 the RXPHE event status bit will 
not generate an interrupt.  When MRXPHE is 1 and the RXPHE event status bit is 1, the 
hardware IRQ interrupt line will be asserted to generate an interrupt. 

MRXDFR

 

 
reg:0E:00 

bit:13

 

Mask receiver data frame ready event.  When MRXDFR is 0 the RXDFR event status bit will 
not generate an interrupt.  When MRXDFR is 1 and the RXDFR event status bit is 1, the 
hardware IRQ interrupt line will be asserted to generate an interrupt. 

MRXFCG

 

 
reg:0E:00 

bit:14

 

Mask receiver FCS good event.  When MRXFCG is 0 the RXFCG event status bit will not 
generate an interrupt.  When MRXFCG is 1 and the RXFCG event status bit is 1, the hardware 
IRQ interrupt line will be asserted to generate an interrupt. 

MRXFCE

 

 
reg:0E:00 

bit:15

 

Mask receiver FCS error event.  When MRXFCE is 0 the RXFCE event status bit will not 
generate an interrupt.  When MRXFCE is 1 and the RXFCE event status bit is 1, the hardware 
IRQ interrupt line will be asserted to generate an interrupt. 

MRXRFSL

 

 
reg:0E:00 

bit:16

 

Mask receiver Reed Solomon Frame Sync Loss event.  When MRXRFSL is 0 the RXRFSL event 
status bit will not generate an interrupt.  When MRXRFSL is 1 and the RXRFSL event status bit 
is 1, the hardware IRQ interrupt line will be asserted to generate an interrupt. 

MRXRFTO

 

 
reg:0E:00 

bit:17

 

Mask Receive Frame Wait Timeout event.  When MRXRFTO is 0 the RXRFTO event status bit 
will not generate an interrupt.  When MRXRFTO is 1 and the RXRFTO event status bit is 1, the 
hardware IRQ interrupt line will be asserted to generate an interrupt. 

MLDEERR

 

 
reg:0E:00 

bit:18

 

Mask leading edge detection processing error event.  When MLDEERR is 0 the LDEERR event 
status bit will not generate an interrupt.  When MLDEERR is 1 and the LDEERR event status 
bit is 1, the hardware IRQ interrupt line will be asserted to generate an interrupt. 

–   
reg:0F:00 

bit:19

 

This bit is reserved. 

MRXOVRR

 

 
reg:0E:00 

bit:20

 

Mask Receiver Overrun event.  When MRXOVRR is 0 the RXOVRR event status bit will not 
generate an interrupt.  When MRXOVRR is 1 and the RXOVRR event status bit is 1, the 
hardware IRQ interrupt line will be asserted to generate an interrupt. 

MRXPTO

 

 
reg:0E:00 

bit:21

 

Mask Preamble detection timeout event.  When MRXPTO is 0 the RXPTO event status bit will 
not generate an interrupt.  When MRXPTO is 1 and the RXPTO event status bit is 1, the 
hardware IRQ interrupt line will be asserted to generate an interrupt. 

MGPIOIRQ

 

 
reg:0E:00 

bit:22

 

Mask GPIO interrupt event.  When MGPIOIRQ is 0 the GPIOIRQ event status bit will not 
generate an interrupt.  When MGPIOIRQ is 1 and the GPIOIRQ event status bit is 1, the 
hardware IRQ interrupt line will be asserted to generate an interrupt. 

MSLP2INIT

 

 
reg:0E:00 

bit:23

 

Mask 

SLEEP

 to 

INIT

 event.  When MSLP2INIT is 0 the SLP2INIT event status bit will not 

generate an interrupt.  When MSLP2INIT is 1 and the SLP2INITevent status bit is 1, the 
hardware IRQ interrupt line will be asserted to generate an interrupt. 

MRFPLLLL

 

 
reg:0E:00 

bit:24

 

Mask RF PLL Losing Lock warning event.  When MRFPLLLL is 0 the RFPLL_LL event status bit 
will not generate an interrupt.  When MRFPLLLL is 1 and the RFPLL_LL event status bit is 1, 
the hardware IRQ interrupt line will be asserted to generate an interrupt. 

MCPLLLL

 

 
reg:0E:00 

bit:25

 

Mask Clock PLL Losing Lock warning event.  When MCPLLLL is 0 the CLKPLL_LL event status 
bit will not generate an interrupt.  When MCPLLLL is 1 and the CLKPLL_LL event status bit is 1, 
the hardware IRQ interrupt line will be asserted to generate an interrupt. 

Summary of Contents for DW1000

Page 1: ... Decawave Ltd 2017 Version 2 12 Page 1 of 242 DW1000 USER MANUAL HOW TO USE CONFIGURE AND PROGRAM THE DW1000 UWB TRANSCEIVER This document is subject to change without notice DW1000 USER MANUAL ...

Page 2: ...1 7 THE DW1000 REGISTER SET 63 7 1 REGISTER MAP OVERVIEW 63 7 2 DETAILED REGISTER DESCRIPTION 65 8 DW1000 CALIBRATION 198 8 1 IC CALIBRATION CRYSTAL OSCILLATOR TRIM 198 8 2 IC CALIBRATION TRANSMIT POWER AND SPECTRUM 200 8 3 IC CALIBRATION ANTENNA DELAY 203 9 OPERATIONAL DESIGN CHOICES WHEN EMPLOYING THE DW1000 206 9 1 OPERATING RANGE 206 9 2 CHANNEL AND BANDWIDTH SELECTION 206 9 3 CHOICE OF DATA R...

Page 3: ...RAME IS RECEIVED 41 FIGURE 18 STATE TRANSITIONS DURING SNIFF MODE 42 FIGURE 19 POWER PROFILE FOR SNIFF WHERE A FRAME IS NOT RECEIVED 43 FIGURE 20 POWER PROFILE FOR SNIFF WHERE A FRAME IS RECEIVED 43 FIGURE 21 POWER PROFILE FOR LOW DUTY CYCLE SNIFF WHERE A FRAME IS NOT RECEIVED 44 FIGURE 22 ESTIMATED RX LEVEL VERSUS ACTUAL RX LEVEL 47 FIGURE 23 DW1000 EXTERNAL SYNCHRONISATION INTERFACE 55 FIGURE 24...

Page 4: ...GC_TUNE3 VALUES 123 TABLE 27 SCALING FACTOR FOR CHANNEL NOISE ENERGY ESTIMATION 124 TABLE 28 REGISTER FILE 0X26 GPIO CONTROL AND STATUS OVERVIEW 128 TABLE 29 REGISTER FILE 0X27 DIGITAL RECEIVER CONFIGURATION OVERVIEW 141 TABLE 30 SUB REGISTER 0X27 02 DRX_TUNE0B VALUES142 TABLE 31 SUB REGISTER 0X27 04 DRX_TUNE1AVALUES 144 TABLE 32 SUB REGISTER 0X27 06 DRX_TUNE1B VALUES144 TABLE 33 SUB REGISTER 0X27...

Page 5: ...BLE 61 DW1000 SUPPORTED UWB CHANNELS AND RECOMMENDED PREAMBLE CODES 215 TABLE 62 FRAME TYPE FIELD VALUES 218 TABLE 63 DESTINATION ADDRESSING MODE FIELD VALUES 220 TABLE 64 SOURCE ADDRESSING MODE FIELD VALUES 220 TABLE 65 TYPICAL CLOCK INDUCED ERRORS IN SS TWR TIME OF FLIGHT ESTIMATION 223 TABLE 66 TYPICAL CLOCK INDUCED ERROR IN SS TWR TIME OF FLIGHT ESTIMATION USING ACTUAL IEEE80 15 4 2011 UWB FRA...

Page 6: ...o entirely at their own risk and agree to fully indemnify Decawave and its representatives against any damages arising out of the use of Decawave products in such safety critical applications Caution ESD sensitive device Precaution should be used when handling the device in order to prevent permanent damage REGULATORY APPROVALS The DW1000 as supplied from Decawave has not been certified for use in...

Page 7: ...hen implementing systems using it Information already contained in the DW1000 data sheet is not reproduced here and it is intended that the reader should use this user manual in conjunction with the DW1000 data sheet The document is divided into a number of sections each of which deals with a particular aspect of the DW1000 as follows Section No Section Name Information covered 2 Overview of the D...

Page 8: ...ides API functions for transmission and reception and for driving the functionalities of the IC The DW1000 driver source code is targeted for the ARM cortex M3 but is readily portable to other microprocessor systems The code comes with a number of demo test applications including a two way ranging application to exercise the API and the features of the DW1000 Clock Periods and Frequencies The chip...

Page 9: ...DW1000 User Manual Decawave Ltd 2017 Version 2 12 Page 9 of 242 Data Rate Where a data rate of 6 8 Mbps is referred to this is equivalent to the 6 81 6 8 Mbps data rate in 1 ...

Page 10: ...perating mode of the SPI is determined when the DW1000 s digital control function is initialised as a result of a device reset or as it is woken up from a sleep state At this time GPIO lines 5 and 6 are sampled and their values act to select the SPI mode It is possible to set the SPI mode within the DW1000 s one time programmable configuration block to avoid needing any external components and lea...

Page 11: ... DW1000 register set Every SPI access transaction header includes a 6 bit register file ID that identifies which register file is being accessed by the transaction Sub addressing within the selected register file allows efficient access to all the parameters within the DW1000 Depending on the sub addressing being used the transaction header is either one two or three octets long These three types ...

Page 12: ... the second octet bit 7 is zero indicating that a further transaction header octet is not present and that the remaining 7 bits of octet 2 are a short sub index into the register file Figure 4 Two octet header of the short indexed SPI transaction The remaining octets of the transaction the transaction body immediately following this two octet header are read from or written to the selected registe...

Page 13: ...e longer the three octet header This example is a write to the transmit data buffer at sub index 0x136 The TX buffer has register file ID of 0x09 Octet 1 of transaction header is thus 0xC9 as bit 7 is 1 to signal a write and bit 6 is 1 indicating a sub address follows The 15 bit sub address has the binary value 000 0001 0011 0110 In octet 2 of the transaction header bit 7 is set to indicate an ext...

Page 14: ...on the setting of the corresponding bit in the Register file 0x0E System Event Mask Register By default on power up all interrupt generating events are masked and interrupts are disabled 2 2 3 General Purpose I O The DW1000 provides 8 GPIO pins These can be individually configured at the user s discretion to be inputs or outputs The state of any GPIO configured as an input can be read and reported...

Page 15: ...EUP INIT RX enabled RX TX RX complete Snooze set Snooze count complete Wakeup Event SNOOZE SLEEP CLKPLL locked TX enabled TX complete DEEPSLEEP 3 3 V rail POR threshold Restore selected AON configuration IDLE Store selected AON configuration SLEEP or DEEPSLEEP Power off N Y N Y Y N Y Y Y Y AUTO SLEEP IRQ Pending N N N N Y Y Y Y N N N N N Y Force to INIT Y ...

Page 16: ... CLKPLL lock time i e at t 5 µs when the automatic switch from the INIT state to the IDLE state is occurring because the switch over of clock source can cause bit errors in the SPI transactions It is possible to return to the INIT state from the IDLE state under register control by selecting the XTAL as the clock source and by disabling what is known as sequencing so the device does not automatica...

Page 17: ...three modes depending on the programmed configuration After the frame transmission is complete the DW1000 will return to the IDLE state unless the ATXSLP bit is set in Sub Register 0x36 04 PMSC_CTRL1 in which case the DW1000 will enter the SLEEP or DEEPSLEEP state automatically as long as no host interrupts are pending Note that it is not possible to be in the TX and RX states simultaneously the D...

Page 18: ...d start POR 2 4 1 SLEEP and DEEPSLEEP In the DW1000 very low power DEEPSLEEP state the IC is almost completely powered down except for a small amount of memory necessary to maintain IC configurations This is the lowest power mode of the IC where the power drain is 100 nA To wake the IC from DEEPSLEEP requires an external agent to assert the WAKEUP input line or the external host microprocessor to ...

Page 19: ...s 2 4 1 2 Configuration register preservation Prior to entering the SLEEP and DEEPSLEEP states and prior to exiting the WAKEUP state the main DW1000 configurations are copied to and from an Always On memory AON Power is maintained to AON memory at all times even in SLEEP and DEEPSLEEP states The copying of configuration data saving or restoring takes about 7 µs to complete The detail of which conf...

Page 20: ...ng user configuration required The default configuration may be summarised as being channel 5 preamble code 4 and mode 2 Channel numbers and preamble codes are as specified in the standard IEEE 802 15 4 2011 1 and mode 2 is as specified in the DW1000 data sheet modes and comprises the following configurations Table 2 Mode 2 Excerpt from DW1000 Data Sheet Operational Modes Table Mode Data Rate PRF ...

Page 21: ...tering FFEN double buffering DIS_DRXB and automatic acknowledgement AUTOACK are all off by default Automatic CRC generation is on and the CRC LFSR is initialized to 0 s FCS_INIT2F Note that CRC generation is selected as part of a transmit command see Register file 0x0D System Control Register External synchronisation and the use of external power amplifiers are deactivated by default see sections ...

Page 22: ...ithm that has been loaded in RAM will execute on every frame reception which in turn will calculate accurate frame time of arrival However the DW1000 needs to load this microcode on power on from a special ROM area in the DW1000 This is done by enabling the LDELOAD bit as part of DW1000 initialisation because after powering up the DW1000 or after exiting SLEEP or DEEPSLEEP states the LDE RAM is em...

Page 23: ...5 7 RF_TXCTRL RF_TXCTRL is not set to the optimum values by default This value should be set for channel 5 according to Table 38 before proceeding to use the default configuration Please see Sub Register 0x28 0C RF_TXCTRL for further information 2 5 5 8 TC_PGDELAY TC_PGDELAY is set to 0xC5 by default which is the incorrect value for channel 5 This value should be set to 0xC0 before proceeding to u...

Page 24: ...00 2 5 5 11 LDOTUNE It is necessary to load the LDOTUNE_CAL value from the OTP if it has been programmed during IC production test calibration To confirm if the LDOTUNE_CAL has been programmed first read the OTP address 0x4 If this reads back as non zero only the first byte needs to be checked then the device has been calibrated To load this value automatically following a wake up from SLEEP or DE...

Page 25: ...guration is carried out in the IDLE state but frame configurations may be carried out during active transmit as described in section 3 5 High Speed Transmission Assuming all other relevant configurations have already been made the host controller initiates the transmission by setting the TXSTRT control bit in Register file 0x0D System Control Register After transmission has been requested the DW10...

Page 26: ...ile 0x0D System Control Register One of the design goals of delayed transmission was that the specified transmission time would be predictable and aligned with the Transmit timestamp This was achieved in that the transmission time specified is the time of transmission of the RMARKER not including the TX antenna delay that is the raw TX time TX_RAWST in Register file 0x17 Transmit Time Stamp before...

Page 27: ...ymbols of preamble while the transmitter is powering up the preamble may not be sent correctly For most use cases this will not be an issue as there is generally ample preamble remaining for good reception However for shorter preamble sequences especially the 64 symbol preamble sequence losing a few symbols can have a performance impact When using delayed transmission with 64 symbol preambles then...

Page 28: ...ta Frames The Data Rate field has the same encoding as used for the IEEE 802 15 4 2011 PHR The frame length field L9 L0 is an unsigned 10 bit integer number that indicates the number of octets in the PSDU from the MAC sub layer Note that the high order bit of the length is transmitted first in time A single bit P0 provides the Preamble Duration field indicating the length of the SYNC portion of th...

Page 29: ...e TX_BUFFER After transmission of the first frame then the host has saved the time needed to write the next data frame and just needs to set the offset and initiate the transmission of the next frame During a data streaming or bulk data transfer then the host controller might divide the TX_BUFFER into two areas of 512 octets each sending from them alternately For acknowledged data transfer then th...

Page 30: ...ng on the application the length of the response may be known before the soliciting message has arrived This is often true for example in two way ranging b Initiate transmission as early as possible For streaming this is as soon as the previous transmission has finished or previous reception has finished RXDFR has been set This is signalled by the activation of the TXFRS Transmit Frame Sent event ...

Page 31: ...S and any address the IC has already consumed the data from which is taken to mean that the data is being written too late for transmission This Transmit Buffer Error condition will cause the DW1000 to ignore the CANSFCS command so the frame is sent with a bad CRC It is signalled by the TXBERR bit in Register file 0x0F System Event Status Register Clearly this is a bad condition that will not help...

Page 32: ...h to allow it But if the PAC is too large for the preamble length then receiver performance will be impaired or fail to work at the extremes e g a PAC of 64 will never receive frames with just 64 preamble symbols Table 6 gives the recommended PAC size configuration to use in the receiver depending on the preamble length being used in the transmitter Table 6 Recommended PAC size Expected preamble l...

Page 33: ...ch defines the RMARKER that is time stamped see section 4 1 6 RX Message timestamp and it marks the change from preamble demodulation to the BPM BPSK demodulation of the PHR and data subsequently It is possible to abort reception if the SFD is not detected within a certain time after preamble is detected This functionality is configured via Sub Register 0x27 20 DRX_SFDTOC This SFD detection timeou...

Page 34: ... Delayed reception see section 4 2 Delayed Receive Long receive frames see section 3 4 Extended Length Data Frames Double buffering see section 4 3 Double Receive Buffer Receive message time stamping see section 4 1 6 RX Message timestamp 4 1 6 RX Message timestamp During frame reception the SFD detection event marking the end of the preamble and the start of the PHR is the nominal point which is ...

Page 35: ...nsmission is in symmetric double sided two way ranging described in APPENDIX 3 Two Way Ranging where it is important to keep the response times the same at both ends to reduce the error in range estimate Minimising the response time also reduces this error and here it is possible for the host microprocessor to be late invoking the delayed TX or RX so that the system clock is beyond the specified s...

Page 36: ...n be enabled in advance of processing the previously received frame This operation will reduce the amount of time for which the receiver may be actively listening for frames on the air but will prevent both buffers being full at the same time and will prevent overflows This simplifies the buffer operation see sections 4 3 3 and 4 3 5 Note When enabling or re enabling the receiver in double buffere...

Page 37: ... same as ICRBP 4 3 3 Operation of double buffering In normal operation the IC will receive a frame into the RX buffer pointed to by ICRBP and when the frame is complete the IC will set the RXFCG interrupting the host and move on to receive into the other buffer of the double buffered swinging set Following this the host system should see this interrupt and service it by reading the received data f...

Page 38: ...ceiver must be reset to exit errored state Unmask Double buffered status bits FCE FCG DFR LDE_DONE Mask Double buffered status bits FCE FCG DFR LDE_DONE to prevent glitch when cleared Rx more frames YES HSRBP ICRBP YES NO Issue TRXOFF command and clear double buffered status bits to prevent spurious RX interrupts NO YES NO Rx more frames EXIT Figure 14 Flow chart for using double RX buffering In F...

Page 39: ...occurs the frame reception in progress will be aborted and assuming RX auto re enable is enabled by RXAUTR the receiver will begin looking for preamble again The overrun condition and the RXOVRR status bit will be cleared as soon as the host issues the HRBPT command Receiver overrun events are also counted in Sub Register 0x2F 0E RX Overrun Error Counter assuming that counting is enabled by the EV...

Page 40: ...t to ensure that if the first listen hits a message missing the preamble then the next listen will see preamble Figure 16 below shows the periodic listening for preamble and a wakeup sequence where the first listening period intersects with the PHR or DATA but where the second listening period allows successful reception Figure 16 Low power listening with two sleep times NOTE Low power listening w...

Page 41: ... the low power listening and will only generate an interrupt when a frame is received Frame filtering can be enabled to further restrict the interrupt to only be generated when a correctly addressed frame is received To save power in such a system the host microprocessor if sufficiently capable can enter a low power state awaiting the DW1000 interrupt to wake it when a frame arrives When a frame i...

Page 42: ... view of the state transitions during SNIFF mode Figure 18 State transitions during SNIFF mode 4 5 1 SNIFF mode In SNIFF mode the DW1000 alternates between the RX on and the IDLE off states To enable SNIFF mode two parameters SNIFF_ONT sniff on time and SNIFF_OFFT the off time need to be configured in Register file 0x1D SNIFF Mode The on duration is programmed in units of PAC these are described i...

Page 43: ... on the second period of RX sampling and the DW1000 completes the reception of a frame Figure 20 Power profile for SNIFF where a frame is received 4 5 2 Low duty cycle SNIFF mode In Low duty cycle SNIFF mode where the off time is larger the DW1000 can be configured to spend this off time in the INIT state which is lower power than the IDLE state used for the off period of a SNIFF This is enabled b...

Page 44: ...opment and in non battery powered devices The LED driving feature is an option on GPIO lines and is configurable via Sub Register 0x26 00 GPIO_MODE Please refer to the register description for details of the supported functionality Access to accumulator of use during product development diagnostics This is provided via Register file 0x25 Accumulator CIR memory Please refer to its description for d...

Page 45: ... that the quality of receive timestamp will be poorer High noise may mean that the real first path is irretrievably buried in the noise Comparing the noise with the First Path Amplitude can give additional indication as to the quality of the first path measurement Where the First Path Amplitude has a large headroom over the noise then the received frame s timestamp is likely to have been determine...

Page 46: ...gister file 0x10 RX Frame Information Register The resultant First Path Power Level in dBm may be compared with the estimated receive power figure calculated as per section 4 7 2 Estimating the receive signal power 4 7 2 Estimating the receive signal power It is possible to calculate an estimate of the receive power level in dBm using the formula Where C the Channel Impulse Response Power value re...

Page 47: ... Estimated RX level versus actual RX level 105 100 95 90 85 80 75 70 65 105 100 95 90 85 80 75 70 65 Estimated RX LEVEL dBm Actual RX LEVEL dBm EstimatedRX LEVEL 16MHz PRF Free Space EstimatedRX LEVEL 64MHz PRF Free Space EstimatedRX LEVEL 64MHz PRF Multipath Actual RX LEVEL ...

Page 48: ...SFCST control is also employed during a throughput maximising response time minimising technique as described in section 3 5 2 TX buffer write while sending 5 2 Frame filtering Frame filtering is a feature of the DW1000 IC that can parse the received data of a frame that complies with the MAC encoding defined in the IEEE 802 15 4 2011 standard identifying the frame type and its destination address...

Page 49: ...t if it is shorter than expected This can make the use of frame types 4 5 6 and 7 problematic and frame filtering may need to be carried out in software if use of frames of type 4 5 6 or 7 with different encodings for frame control bits affecting the header length is planned The frame control bits concerned are the address mode fields and the PID compression field The frame version field must be 0...

Page 50: ...tomatic acknowledgement functionality only operates when frame filtering is enabled and automatic acknowledgement is enabled In order for automatic acknowledgement to operate Frame filtering must be enabled and the received data or MAC command frame must be correctly addressed and pass through the receive frame filtering see section 5 2 Frame filteringfor details of frame filtering configuration T...

Page 51: ... used to determine the preamble length of the ACK Table 9 presents the preamble lengths used for the ACK frame in extended length frame mode as a function of the RXPACC field Table 9 Auto ACK preamble length selection in extended length frames mode PSR accumulated and reported in the RXPACC value Resultant Preamble Length of auto ACK Less than 17 16 Between 17 and 32 32 Between 33 and 64 64 Betwee...

Page 52: ...tart up or reconfiguration of channel parameters The most efficient way to ensure the SFD sequence is correctly initialised is to simultaneously initiate and abort a transmission thereby forcing the SFD initialisation This can be done by writing to the the system control register Register file 0x0D System Control Register with both the transmission startbit TXSTRT and the transceiver off bit TRXOF...

Page 53: ...nowledgement process to complete In this situation when automatic acknowledgement is enabled and the AAT bit is observed as set to avoid waiting for the acknowledgement process to complete and TXFRS to be set the Acknowledgment request field in the frame control section of the MAC header of the received frame as described in Section 11 2 4 should be checked to confirm that the current frame has ac...

Page 54: ...DW1000 User Manual Decawave Ltd 2017 Version 2 12 Page 54 of 242 frame to be overwritten or other behaviour such as receiver timeouts resulting from the device being in the RX state rather than in IDLE ...

Page 55: ...ied on the EXTCLK pin The SYNC input pin is sampled on the rising edge of EXTCLK Refer to the DW1000 datasheet for setup and hold times of the SYNC pin The SYNC input provides a common reference point in time to synchronise the DW1000 with the accuracy necessary to achieve high resolution location estimation 6 1 1 One Shot Timebase Reset OSTR Mode One Shot Timebase Reset OSTR mode allows a reset t...

Page 56: ...n OSTS mode OSTS mode provides for the transmission of a frame at a well defined time relative to the assertion of the SYNC DW1000 input This time will vary slightly per part typically 12 ps but may vary up to 3 ns across process for all parts This feature will be used where a local master locationing device is using the DW1000 as a slave to provide additional location data Calibration can be empl...

Page 57: ...RL1 register see Sub Register 0x36 04 PMSC_CTRL1 In normal operation a ranging timestamp is calculated based on the DW1000 internal timebase see section 4 1 6 RX Message timestamp The timebase counter is captured at the receive event RMARKER and a number of offset values are combined with this capture value to give the ranging timestamp When timestamping the receive event relative to an external t...

Page 58: ...priately This mode of operation utilises the DW1000 pins EXTPA EXTTXE and EXTRXE as configured via the fields MSGP4 MSGP5 and MSGP6 in Sub Register 0x26 00 GPIO_MODE Care should be taken when using this feature to ensure that necessary regulatory requirements have been fulfilled There is a separate application note giving details of the external power amplification This includes the circuit diagra...

Page 59: ...001 LOT ID 28 bits DecawaveTest 0x008 2 Vmeas 3 7 V Vmeas 3 3 V DecawaveTest 0x009 1 1 Tmeas Ant Cal Tmeas 23 C Customer Deca wave Test 0x00A 0 Reserved 0x00B 4 Reserved 0x00C 2 Reserved 0x00D 4 Reserved 0x00E 4 Reserved 0x00F 4 Reserved 0x010 4 CH1 TX Power Level PRF 16 Customer 0x011 4 CH1 TX Power Level PRF 64 Customer 0x012 4 CH2 TX Power Level PRF 16 Customer 0x013 4 CH2 TX Power Level PRF 64...

Page 60: ...requires a number of setup steps to be carried out in sequence Optimal programming requires that the VDDIO pin be driven to 3 8 V or the VDDIOA pin if access to VDDIO is not available The table below outlines the programming steps to place the OTP into its programming state and to programme a single location Table 12 Register accesses required to program the OTP Step Number Instruction Register Ad...

Page 61: ...e address and data values in the registers will still be valid and as such do not require re programming During the programming stages the OTP is configured to stress the read back circuits to their limits This may result in continuous read verify failures In the event that 10 attempts have been made to programme a location then a final read verify is recommended after a full IC reset this will re...

Page 62: ...sensors Step Number Instruction Register Address Data Length Bytes Data Write Read 1 Write Sub Register 28 11 1 0x80 2 Write Sub Register 28 12 1 0x0A 3 Write Sub Register 28 12 1 0x0F 4 Write Register 2A 00 1 0x01 5 Write Register 2A 00 1 0x00 6 Read Register 2A 03 1 8 bit Voltage reading 7 Read Register 2A 04 1 8 bit Temperature reading When in the ADC is configured for automatic operation on wa...

Page 63: ...ister Note When writing to any of the DW1000 registers care must be taken not to write beyond the published length of the selected register and not to write to any of the reserved register locations Doing so may cause the device to malfunction Table 15 Register map overview ID Length octets Type Mnemonic Description 0x00 4 RO DEV_ID Device Identifier includes device type and revision info 0x01 8 R...

Page 64: ...MEM Read access to accumulator data 0x26 44 RW GPIO_CTRL Peripheral register bus 1 access GPIO control 0x27 44 RW DRX_CONF Digital Receiver configuration 0x28 58 RW RF_CONF Analog RF Configuration 0x29 Reserved 0x2A 52 RW TX_CAL Transmitter calibration block 0x2B 21 RW FS_CTRL Frequency synthesiser control block 0x2C 12 RW AON Always On register set 0x2D 18 RW OTP_IF One Time Programmable Memory I...

Page 65: ...ters are 4 octets long the default presentation of the register values is as a 32 bit value This may be sub divided into fields of various bit widths down to single bit values It should be noted that when reading these values via the SPI interface the octets are output least significant octet first Also of note is the fact that the indexed addressing modes allow individual octets to be accessed a ...

Page 66: ...REV reg 00 00 bits 3 0 Revision This number will be updated for minor corrections and changes in operation VER reg 00 00 bits 7 4 Version This number will be updated if a new version is produced that has significant differences from the previous version MODEL reg 00 00 bits 15 8 The MODEL identifies the device The DW1000 is device type 0x01 RIDTAG reg 00 00 bits 31 16 Register Identification Tag I...

Page 67: ...OTP Memory Interface overview gives an overview of OTP contents and addresses During DW1000 initialisation or upon waking up from sleep mode the Register file 0x01 Extended Unique Identifier register value is loaded from its OTP memory area After this the EUI register value may be overwritten by the host system if necessary Certain IEEE 802 15 4 defined frames use a 64 bit source address The softw...

Page 68: ...al area network PAN the PAN coordinator node determines the PAN Identifier for the network and assigns it and short 16 bit addresses to devices nodes associating with the PAN The nodes in the PAN then should at the MAC layer use their assigned short address as the source address and include it along with the PAN Identifier in the frames they transmit When a node receives a frame it should only pro...

Page 69: ...gister map register file 0x04 is the system configuration register This is a bitmapped register Each bit field is separately identified and described below The System Configuration register contains the following bitmapped sub fields REG 04 00 SYS_CFG System Configuration bit map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AACKPEND AUTOACK RXAUTR RXWTOE RX...

Page 70: ...owledgment frames will be ignored Section 5 2 describes frame filtering in more detail FFAM reg 04 00 bit 5 Frame Filtering Allow MAC command frame reception IEEE 802 15 4 2011 frames begin with three frame type bits b3 to b0 for MAC command frames these are binary 011 When FFAM is set to 1 MAC command frames will be accepted assuming all other frame filtering rules are passed and when FFAM is cle...

Page 71: ...e target system When SPI_EDGE is 0 the DW1000 uses the sampling edge to launch MISO data This setting should give the highest rate operation When SPI_EDGE is 1 the DW1000 uses the opposite edges to launch the data This setting may give a more robust operation DIS_FCE reg 04 00 bit 11 Disable frame check error handling This might be of use for protocols using a different encoding scheme for error h...

Page 72: ...ion of PHR type to be one of two options The default setting gives IEEE standard PHR encoding and a maximum data payload of 127 octets The other option enables the proprietary long frames mode which allows a data payload of up to 1023 octets In this mode the PHR encoding does not follow the IEEE standard For successful communications between two nodes both must be configured for the same PHR mode ...

Page 73: ...ause of some error condition for example an error in the PHY header as reported by the RXPHE event status bit in Register file 0x0F System Event Status Register In such cases if the host wants to re enable the receiver it must do it explicitly using the RXENAB bit in Register file 0x0D System Control Register The operation when RXAUTR 1 is as follows a Double buffered mode After a frame reception ...

Page 74: ...8481 seconds b In sleep modes the system time counter is disabled and this register is not updated 7 2 9 Register file 0x07 Reserved ID Length octets Type Mnemonic Description 0x07 Reserved this register file is reserved Register map register file 0x07 is reserved for future use Please take care not to write to this register as doing so may cause the DW1000 to malfunction 7 2 10 Register file 0x08...

Page 75: ...ails of this non standard mode R Reserved Bits 12 11 10 are reserved for future expansion They should be set to zero TXBR reg 08 00 bits 14 13 Transmit Bit Rate This sets the user bit rate for the data portion of the frame as follows Bit 14 Bit 13 Bit Rate 0 0 110 kbps 0 1 850 kbps 1 0 6 8 Mbps 1 1 reserved TR reg 08 00 bit 15 Transmit Ranging enable This bit has no operational effect on the DW100...

Page 76: ...se system performance The resultant preamble lengths depend the setting of both PE and TXPSR above Table 16 below lists the useful preamble lengths that can be selected Table 16 Preamble length selection Bit 19 Bit 18 Bit 21 Bit 20 TXPSR PE Preamble Length 0 1 0 0 64 0 1 0 1 128 0 1 1 0 256 0 1 1 1 512 1 0 0 0 1024 1 0 0 1 1536 1 0 1 0 2048 1 1 0 0 4096 The bit numbers quoted above are the bit num...

Page 77: ...ap register file 0x09 is the transmit data buffer Data from the transmit buffer is transmitted during the data payload portion of the transmitted frame Section 3 Message Transmission discusses the basics of frame transmission and details the various parts of the TX frame The general procedure is to write the data frame for transmission into the TX_BUFFER set the frame length and other details in t...

Page 78: ...flexibility to the system designer in selecting the microprocessor to optimise the solution The frame wait timeout is enabled by the RXWTOE bit in Register file 0x04 System Configuration When the receiver is enabled and begins hunting for the preamble sequence and RXWTOE is set then the frame wait timeout counter starts counting the timeout period programmed Thereafter assuming no action is taken ...

Page 79: ...FWTO specified period and if no data is received before this RX Frame Wait Timeout timer expires then the receiver is returned to its idle state and the timeout is signalled by the RXRFTO event status bit in Register file 0x0F System Event Status Register reg 0C 00 bits 31 16 These bits are reserved and should always be written as zero Note The frame wait timeout may also be employed with double b...

Page 80: ...ed the DW1000 will not append the FCS to the data frame but instead fetches the two bytes from the TX buffer The frame length is determined by the TFLEN field of Register file 0x08 Transmit Frame Control So when SFCST is clear TFLEN 2 frame length minus two octets are fetched and sent from the TX buffer and the final two octets sent are the automatically generated FCS bytes And when SFCST is set T...

Page 81: ...g TXDLYS allows this time to be predicted pre calculated and embedded into the final message itself This may save the need for an additional message interchange which will give a power saving and save time too Embedding the TX time in this way may also reduce the number of messages in a wireless clock synchronisation scheme CANSFCS reg 0D 00 bit 3 Cancel Suppression of auto FCS transmission on the...

Page 82: ...or Receive Time When the user wants to control the time of turning on the receiver the turn on time is programmed into DX_TIME and then both RXDLYE and RXENAB should be set to correctly invoke the delayed receiving feature The DW1000 then precisely controls the RX turn on time so that it is ready to receive the first symbol of preamble at the specified DX_TIME start time In cases when the received...

Page 83: ...0 bit 4 Mask transmit frame begins event When MTXFRB is 0 the TXFRB event status bit will not generate an interrupt When MTXFRB is 1 and the TXFRB event status bit is 1 the hardware IRQ interrupt line will be asserted to generate an interrupt MTXPRS reg 0E 00 bit 5 Mask transmit preamble sent event When MTXPRS is 0 the TXPRS event status bit will not generate an interrupt When MTXPRS is 1 and the ...

Page 84: ...terrupt When MRXRFTO is 1 and the RXRFTO event status bit is 1 the hardware IRQ interrupt line will be asserted to generate an interrupt MLDEERR reg 0E 00 bit 18 Mask leading edge detection processing error event When MLDEERR is 0 the LDEERR event status bit will not generate an interrupt When MLDEERR is 1 and the LDEERR event status bit is 1 the hardware IRQ interrupt line will be asserted to gen...

Page 85: ...tem Event Status Register ID Length octets Type Mnemonic Description 0x0F 5 SRW SYS_STATUS System Event Status Register Register map register file 0x0F is the system event status register SYS_STATUS It contains status bits that indicate the occurrence of different system events or status changes It is possible to enable particular events as interrupt sources by employing the SYS_MASK Register file...

Page 86: ...at its maximum rate also The CPLOCK bit is cleared by writing a 1 to it The clock PLL lock status is also available via the CPLLLOCK status bit in Sub Register 0x28 2C RF_STATUS Note The PLLLDT bit in Register file 0x24 00 EC_CTRL should be set to ensure reliable operation of this CPLOCK bit ESYNCR reg0F 00 bit 2 External Sync Clock Reset This event status bit is set when the system counter is res...

Page 87: ...enable including those caused by the RXAUTR auto re enable RXSFDD reg 0F 00 bit 9 Receiver SFD Detected This event status bit is set to indicate that the receiver has detected the SFD sequence and is moving on to decode the PHR Section 4 Message Reception gives details of the frame reception process The RXSFDD bit can be cleared explicitly by writing a 1 to it It is also automatically cleared by t...

Page 88: ...o validate the receive timestamp information In order to ensure that the receive timestamp information is valid before any receive interrupt processing takes place the setting of RXDFR is delayed until the LDE adjustments of the timestamp have completed at which time the LDEDONE event status bit will be set or possibly LDEERR The RXDFR event status flag bit is included in the RX double buffered sw...

Page 89: ...FTO bit is automatically cleared at the next receiver enable It can also be cleared explicitly by writing a 1 to it Receive frame wait timeout events are also counted in Sub Register 0x2F 14 RX Frame Wait Timeout Event Counter as long as counting is enabled by the EVC_EN bit in Sub Register 0x2F 00 Event Counter Control LDEERR reg 0F 00 bit 18 Leading edge detection processing error A large part o...

Page 90: ...ed to indicate that wake up has occurred and the DW1000 is in the IDLE state RFPLL_LL reg 0F 00 bit 24 RF PLL Losing Lock This event status bit is set is set to indicate that the RFPLL is having locking issues This should not happen in healthy devices operating in their normal range Its occurrence may indicate a bad configuration a faulty part or a problem in the power or clock inputs to the devic...

Page 91: ...suming counting is enabled by the EVC_EN bit in Sub Register 0x2F 00 Event Counter Control TXBERR reg 0F 00 bit 28 Transmit Buffer Error The TXBERR event status flag bit indicates that a write to a transmitted data buffer location has occurred whilst CRC was suppressed Section 3 5 High Speed Transmission describes the DW1000 features for maximising data throughput One technique involves writing th...

Page 92: ...d by the RXAUTR auto re enable RXPREJ reg 0F 04 bit 1 Receiver Preamble Rejection This is a low level event status flag which is probably not of interest to the host system It was used during the IC implementation as part of tuning the preamble detection algorithm In the DW1000 preamble detection a two stage process where preamble is initially seen and then has to be confirmed as continuing for a ...

Page 93: ... Field Description of fields within Register file 0x10 RX Frame Information Register RXFLEN reg 10 00 bits 6 0 Receive Frame Length This value is copied from the PHR of the received frame when a good PHR is detected when the RXPHD status bit is set The frame length from the PHR is used in the receiver to know how much data to receive and decode and where to find the FCS CRC to validate the receive...

Page 94: ...96 The bit numbers quoted above are the bit numbers in the RX_FINFO register Where preamble length is not predetermined and hard coded in the application the received preamble length information may be used to select the preamble length for any response message by copying RXNSPL and RXPSR fields into the PE and TXPSR configurations respectively This value is updated when a good PHR is detected whe...

Page 95: ...hen a good PHR is detected when the RXPHD status bit is set The channel accumulation sometimes includes the SFD symbols all except the last two Signal power calculations using RXPACC for the number of symbols sometimes need to be adjusted for the SFD symbols accumulated See section 4 7 for calculations using RXPACC The RXPACC counter will saturate when preamble is found by the receiver and the CIR...

Page 96: ...e received frame is available in the received buffer Assuming successful reception of a good frame the full length of received data as reported by the RXFLEN and RXFLE fields of Register file 0x10 RX Frame Information Register will be available in the RX_BUFFER beginning at offset 0 Note since the reported length includes the FCS the host system will probably choose not to read these final two oct...

Page 97: ...RX timestamp FP_AMPL2 reg 12 00 bits 31 16 First Path Amplitude point 2 This is a 16 bit value that is part of reporting the magnitude of the leading edge signal seen in the accumulator data memory during the LDE algorithm s analysis The amplitude of the sample reported in the FP_AMPL2 parameter is the magnitude of the accumulator tap at the index 2 beyond the integer portion of the rising edge FP...

Page 98: ...me Tracking Interval is in the RX double buffered swinging set See section 4 3 Double Receive Buffer for more details The RX_TTCKI register contains the following sub fields which are updated when a frame demodulation is completed successfully REG 13 00 RX_TTCKI Receiver Time Tracking Interval 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXTTCKI 0 Field Des...

Page 99: ...e local receiver s clock by this 7 ppm amount Example b Say RXTOFS is reported as 0x7FF5C and RXTTCKI is 0x01f00000 then this gives a clock offset of 164 32505856 which is 5 045E 06 or 5 ppm offset So the remote transmitter s clock is running slower than the local receiver s clock by this 5 ppm amount Bits marked are reserved and should always be written as zero RSMPDEL reg 14 00 bits 31 24 This 8...

Page 100: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX_RAWST low 24 bits of 40 bit value FP_AMPL1 high 8 bits of 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG 15 0C RX_TIME Receive Time Stamp Octets 12 to 13 16 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX_RAWST high 16 bits of 40 bit value 0 0 0 0 0 0 0 ...

Page 101: ...e magnitude of the leading edge signal seen in the accumulator data memory during the LDE algorithm s analysis The amplitude of the sample reported in the FP_AMPL1 parameter is the magnitude of the accumulator tap at the index 3 beyond the integer portion of the rising edge FP_INDEX reported in this register The FP_AMPL1 amplitude value can be used in conjunction with the FP_AMPL2 and FP_AMPL3 val...

Page 102: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 The sub fields of Register file 0x17 Transmit Time Stamp are laid out above in a map that is 32 bits wide It is possible to read a variable number of bytes any byte index The individual sub fields are described below Field Description of fields within Register file 0x17 Transmit Time Stamp TX_STAMP reg 17 00 bits 39 0 This 40 bit 5 octet field reports the fully adjusted...

Page 103: ...Register map register file 0x1A is a configuration register used for specifying turn around times for DW1000 to use when automatically switching between TX mode and RX modes The ACK_RESP_T register contains the following bitmapped sub fields REG 1A 00 ACK_RESP RX Frame Information 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACK_TIM W4R_TIM 0 0 0 0 0 0 The ...

Page 104: ...the 6 8 Mbps data rate where preamble sequences are generally short and losing even a few preamble symbols could potentially compromise ACK reception Where the W4R_TIM parameter is larger than zero the ACK_TIM setting should be increased also to ensure that none of the frame is sent before the remote receiver is listening Bits marked are reserved and should always be written as zero 7 2 29 Registe...

Page 105: ...time specified in µs This parameter is specified in units of approximately 1 µs or 128 system clock cycles A value of zero will disable SNIFF Mode A non zero value will enable SNIFF Mode and select how long the receiver is turned off for during the preamble hunt Please refer to the SNIFF_ONT description above for more details of this feature As an example with a 1024 preamble length a roughly 50 d...

Page 106: ...mpression of the TX signal Good isolation requires seperate PCB tracks to each of these pins 7 2 31 2 Smart Transmit Power Control This functionality applies when the Disable Smart TX Power Control bit DIS_STXP in Register file 0x04 System Configuration is zero not set The power output regulations typically specify a transmit power limit of 41 3 dBm in each 1 MHz bandwidth and generally measure th...

Page 107: ...e and frame length criteria required for a boost i e the frame duration is more than 0 5 ms It is also the power setting used for the PHR portion of the frame for all of the other three cases Section 7 2 31 1 Units of TX Power Control details the programming of this value BOOSTP500 reg 1E 00 bits 15 8 This value sets the power applied to the preamble and data portions of the frame during transmiss...

Page 108: ...mbols and Frame Length of 23 bytes At 64 MHz PRF a 9 dB power boost can be configured here so long as the external system keeps the frame rate below 1 frame per millisecond to ensure the power boost is not breaking regulations At 16 MHz PRF the power boost should be set to the same 6 dB value used for the BOOSTP250 configuration to avoid exceeding peak power regulations Section 7 2 31 1 Units of T...

Page 109: ... high for the manual use case In order to comply with regional spectrum regulations it should be reduced to a level appropriate for the external RF circuitry and compliance to the regulations The Table 19 values apply when smart TX power is being employed i e the Disable Smart TX Power Control bit DIS_STXP in Register file 0x04 System Configuration is zero not set and the Table 20 values apply whe...

Page 110: ...led 7 2 32 Register file 0x1F Channel Control ID Length octets Type Mnemonic Description 0x1F 4 RW CHAN_CTRL Channel Control Register Register map register file 0x1F is the channel control register This is used to select transmit and receive channels and configure preamble codes and some related parameters The fields of the Channel Control Register are defined as follows REG 1F 00 CHAN_CTRL Channe...

Page 111: ... according to the operating channel For details of centre frequencies and preamble codes for the supported channels please refer to section 10 5 UWB channels and preamble codes RX_CHAN reg 1F 00 bits 7 4 This selects the receive channel Supported channels are 1 2 3 4 5 and 7 Other values should not be used Both RX_CHAN and TX_CHAN above should be set to the same value Full selection of RX channel ...

Page 112: ...le 21 Recommended SFD sequence configurations for best performance Data Rate DWSFD reg 1F 00 bit 17 TNSSFD reg 1F 00 bit 20 RNSSFD reg 1F 00 bit 21 SFD_LENGTH reg 21 00 bits 0 7 Description 6 8 Mbps 0 0 0 x When the DW1000 is operating at 6 8 Mbps this programming selects the standard IEEE 8 symbol SFD which gives sufficient robustness since the data is already the weakest part of the frame 850 kb...

Page 113: ...nce used in the transmitter has to be programmed to match the SFD sequence being hunted for in the receiver The TNSSFD bit enables the use of user programmed non standard SFD sequence in the transmitter For more details please refer to Register file 0x21 User defined SFD sequence TX_PCODE reg 1F 00 bits 26 22 This field selects the preamble code used in the transmitter The user should select the p...

Page 114: ... file 0x21 User defined SFD sequence are described below giving the index within the register file and defining the parameter at that index NOTE Designing SFD sequences is a complicated task beyond the scope of this manual Where improved performance is desired and standard compliance is not required it is recommend to use the Decawave defined non standard SFD enabled by setting the DWSFD bit Only ...

Page 115: ...perating at 850 kbps this programming selects a Decawave defined non standard 8 symbol SFD which is stronger than the standard defined SFD but still a little weaker that the data Hence our recommendation of the 16 symbol SFD defined Table 21 for best performance at 850 kbps 6 8 Mbps or 850 kbps 0 1 1 8 to 16 When the DW1000 is operating at 6 8 Mbps or 850 kbps this programming selects the use of a...

Page 116: ...a for the receive SFD sequence for the second 8 symbol intervals The values here are used when SFD_LENGTH is greater than 8 Where SFD_LENGTH is less than 16 the low order bits are applicable up to the specified length 7 reg 21 07 RX_SSFD_SGNL Symbols 7 0 This field sets the short SFD polarity data for the receive SFD sequence for the first 8 symbol intervals The low order bits define the part of t...

Page 117: ...4 symbol SFD magnitude data for the receive SFD sequence for symbol intervals 23 to 16 28 reg 21 1C RX_LSFD_MAG3 Symbols 31 24 This field sets the long 64 symbol SFD magnitude data for the receive SFD sequence for symbol intervals 31 to 24 29 reg 21 1D RX_LSFD_MAG4 Symbols 39 32 This field sets the long 64 symbol SFD magnitude data for the receive SFD sequence for symbol intervals 39 to 32 30 reg ...

Page 118: ...bps 0 0 0 x When the DW1000 is operating at 6 8 Mbps this programming selects the standard IEEE 8 symbol SFD which gives sufficient robustness since the data is already the weakest part of the frame 850 kbps 1 1 1 16 The standard IEEE 8 symbol SFD is weaker than data at 850 kbps When the DW1000 is operating at 850 kbps this programming selects a Decawave defined non standard 16 symbol SFD which re...

Page 119: ...SFD improving the performance in 110 kbps mode Table 22 below presents additional SFD sequence programming options Note The selection of SFD sequences other than the IEEE 802 15 4 2011 UWB standard compliant SFD sequence may improve performance but will of course make it impossible to interwork with a device configured to use the standard defined SFD or with a third party devices using the standar...

Page 120: ... 17 TNSSFD reg 1F 00 bit 20 RNSSFD reg 1F 00 bit 21 SFD_LENGTH reg 21 00 bits 0 7 Description 850 kbps 0 0 0 x This programming selects the 8 symbol SFD as defined in the IEEE 802 15 4 standard when operating at 850 kbps 110 kbps 0 0 0 x This programming selects the 64 symbol SFD as defined in the IEEE 802 15 4 standard when operating at 110 kbps ...

Page 121: ...the DW1000 is operating at 850 kbps this programming selects a Decawave defined non standard 8 symbol SFD which is stronger than the standard defined SFD but still a little weaker that the data Hence our recommendatio n of the 16 symbol SFD defined Table 21 for best performance at 850 kbps ...

Page 122: ...figurable in the range 8 to 16 symbols In this mode the user is responsible for correctly programming the SFD sequence in Register file 0x21 User defined SFD sequence 110 kbps 0 1 1 x When the DW1000 is operating at 110 kbps this selects the use of a user configured SFD with fixed length of 64 symbols In this mode the user is responsible for correctly programming the SFD sequence in Register file ...

Page 123: ...on 0x23 33 RW AGC_CTRL Automatic Gain Control configuration and control Register map register file 0x23 is for configuration and control of the receiver gain control block It contains a number of sub registers some of which need user control Table 23 gives an overview of the sub registers within Register file 0x23 AGC configuration and control and these sub registers are individually described in ...

Page 124: ... disable the AGC measurement function The AGC measurement function might be used as an energy measurement for an Energy Scan as part of determining what channel to use When DIS_AM bit is clear and the receiver is enabled the AGC will settle on an estimate of the background energy level and the result will be available via the EDG1 and EDV2 values in Sub Register 0x23 1E AGC_STAT1 To save power in ...

Page 125: ... 7 2 36 4 Sub Register 0x23 06 AGC_RES2 ID Length octets Type Mnemonic Description 23 06 6 AGC_RES2 Reserved area 2 Register file 0x23 AGC configuration and control sub register 0x06 is a reserved area Please take care not to write to this area as doing so may cause the DW1000 to malfunction 7 2 36 5 Sub Register 0x23 0C AGC_TUNE2 ID Length octets Type Mnemonic Description 23 0C 4 RW AGC_TUNE2 AGC...

Page 126: ...AGC Please ensure to program it to the value given in Table 26 below Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction Table 26 Sub Register 0x23 12 AGC_TUNE3 values Value to program to Sub Register 0x23 12 AGC_TUNE3 0x0035 7 2 36 8 Sub Register 0x23 14 AGC_RES4 ID Length octets Type Mnemonic Description 23 14 10 AGC_RES4 Reserved area 4 Re...

Page 127: ...urement EDV2 can be used in conjunction with the EDG1 value to give a measure of the background in band noise energy level This might be used for an Energy Detect ED channel scan as part of implementing the IEEE 802 15 4 standard s MLME SCAN request primitive The noise energy level is given by combining EDG1 and EDV2 value as described in Figure 27 below reg 23 1E These bits are reserved Combining...

Page 128: ...er EC_CTRL The EC_CTRL register is used to configure the external synchronisation mode The EC_CTRL register contains the following sub fields REG 24 00 EC_CTRL External clock synchronisation counter configuration 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSTRM WAIT PLLLDT OSRSM OSTSM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The fie...

Page 129: ...e fields of the EC_RXTC register identified above are individually described below Field Description of fields within Sub Register 0x24 04 EC_RXTC RX_TS_EST reg 24 04 bits 31 0 External clock synchronisation counter captured on RMARKER See section 6 1 3 One Shot Receive Synchronisation OSRS Mode 7 2 37 3 Sub Register 0x24 08 EC_GOLP ID Length octets Type Mnemonic Description 24 08 4 RO EC_GOLP Ext...

Page 130: ...diagnostic purposes The accumulator contains complex values a 16 bit real integer and a 16 bit imaginary integer for each tap of the accumulator each of which represents a 1 ns sample interval or more precisely half a period of the 499 2 MHz fundamental frequency The span of the accumulator is one symbol time This is 992 samples for the nominal 16 MHz mean PRF or 1016 samples for the nominal 64 MH...

Page 131: ...at sub index the read begins at 7 2 39 Register file 0x26 GPIO control and status ID Length octets Type Mnemonic Description 0x26 44 RW GPIO_CTRL Peripheral register bus 1 access GPIO control Register map register file 0x26 is concerned with the use of the GPIO It contains a number of sub registers An overview of these is given by Table 28 Each of these sub registers is separately described in the...

Page 132: ...value When operating as the RXOKLED driver the output is asserted briefly when the receiver completes the reception of a frame with a good FCS CRC The on time for the RXOKLED depends on the blink time set in Sub Register 0x36 28 PMSC_LEDC Note Lighting LEDs will drain power in battery powered applications MSGP1 reg 26 00 bits 9 8 Mode Selection for GPIO1 SFDLED 00 The pin operates as GPIO1 This is...

Page 133: ...is is the default reset state 01 The pin operates as the EXTTXE output 10 Reserved Do not select this value 11 Reserved Do not select this value Refer to section 6 2 External Power Amplification for further information on the use of EXTTXE MSGP6 reg 26 00 bits 19 18 Mode Selection forGPIO6 EXTRXE Allowed values of MSGP6 are 00 The pin operates as GPIO6 This is the default reset state 01 The pin op...

Page 134: ...s the pin is an output The GDP bits and their corresponding GDM mask bits are arranged with four GPIO per octet to allow a single octet write to change direction of an individual GPIO The GPIO_DIR register contains the following sub fields REG 26 08 GPIO_DIR GPIO Direction control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GDM8 GDP8 GDM7 GDM6 GDM...

Page 135: ...octets Type Mnemonic Description 26 0C 4 RW GPIO_DOUT GPIO Data Output register Register file 0x26 GPIO control and status sub register 0x0C is the GPIO data output register The GPIO_DOUT register applies to the GPIO pins when they are selected to operate as GPIO outputs via the GPIO_MODE and GPIO_DIR registers It contains a bit for each GPIO pin to individually select the data to output on the GP...

Page 136: ...e of 1 in that write operation GOP1 bit 1 Output state setting for GPIO1 See GOP0 GOP2 bit 2 Output state setting for GPIO2 See GOP0 GOP3 bit 3 Output state setting for GPIO3 See GOP0 GOM0 reg 26 0C bit 4 Mask for setting GPIO0 output state When writing to GOP0 to select state of the GPIO0 output the value of GOP0 is only changed if this GOM0 mask bit has a value of 1 for the write operation GOM0 ...

Page 137: ...o 1 enables the corresponding GPIO input as an interrupt source a value of 0 disables that interrupt When a GPIO interrupt is triggered it is signalled to the host via the GPIOIRQ event status bit in Register file 0x0F System Event Status Register The bits of the GPIO_IRQE register are as following REG 26 10 GPIO_IRQE GPIO Interrupt Enable register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1...

Page 138: ...G 26 14 GPIO_ISEN GPIO Interrupt Sense Selection register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GISEN8 GISEN7 GISEN6 GISEN5 GISEN4 GISEN3 GISEN2 GISEN1 GISEN0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The bits of the GPIO_ISEN register identified above are individually described below Field Description of fields within Sub Regis...

Page 139: ... REG 26 18 GPIO_IMODE GPIO Interrupt Mode selection register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GIMOD8 GIMOD7 GIMOD6 GIMOD5 GIMOD4 GIMOD3 GIMOD2 GIMOD1 GIMOD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The bits of the GPIO_IMODE register identified above are individually described below Field Description of fields within Sub R...

Page 140: ...h Edge selection register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GIBES8 GIBES7 GIBES6 GIBES5 GIBES4 GIBES3 GIBES2 GIBES1 GIBES0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The bits of the GPIO_IBES register identified above are individually described below Field Description of fields within Sub Register 0x26 1C GPIO_IBES GIBES0 reg...

Page 141: ...l persists then clearing the latch will be ineffective since the interrupt will occur again immediately The GPIO_ICLR register contains a bit for each GPIO pin as follows REG 26 20 GPIO_ICLR GPIO Interrupt latch clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GICLR8 GICLR7 GICLR6 GICLR5 GICLR4 GICLR3 GICLR2 GICLR1 GICLR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T...

Page 142: ...he kilohertz clock The de bounce filter is active when a state change of the GPIO input needs to persist for two cycles of this clock before it will be seen by the interrupt handling logic The GPIO_IDBE register contains a bit for each GPIO pin as follows REG 26 24 GPIO_IDBE GPIO Interrupt De Bounce Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GIDBE8...

Page 143: ...ster file 0x26 GPIO control and status sub register 0x28 allows the raw state of the GPIO pin to be read The GPIO_RAW register contains a bit for each GPIO pin as follows REG 26 28 GPIO_RAW GPIO raw state 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRAWP8 GRAWP7 GRAWP6 GRAWP5 GRAWP4 GRAWP3 GRAWP2 GRAWP1 GRAWP0 0 0 0 0 0 0 0 0 0 The bits of the GPIO_RAW reg...

Page 144: ...egister file 0x27 Digital receiver configuration overview OFFSET in Register 0x27 Mnemonic Description 0x02 DRX_TUNE0b Digital Tuning Register 0b 0x04 DRX_TUNE1a Digital Tuning Register 1a 0x06 DRX_TUNE1b Digital Tuning Register 1b 0x08 DRX_TUNE2 Digital Tuning Register 2 0x20 DRX_SFDTOC SFD timeout 0x24 DRX_PRETOC Preamble detection timeout 0x26 DRX_TUNE4H Digital Tuning Register 4H 0x2C RXPACC_N...

Page 145: ...mance Data Rate DWSFD reg 1F 00 bit 17 TNSSFD reg 1F 00 bit 20 RNSSFD reg 1F 00 bit 21 SFD_LENGTH reg 21 00 bits 0 7 Description 6 8 Mbps 0 0 0 x When the DW1000 is operating at 6 8 Mbps this programming selects the standard IEEE 8 symbol SFD which gives sufficient robustness since the data is already the weakest part of the frame 850 kbps 1 1 1 16 The standard IEEE 8 symbol SFD is weaker than dat...

Page 146: ... the 16 symbol SFD defined Table 21 for best performance at 850 kbps 6 8 Mbps or 850 kbps 0 1 1 8 to 16 When the DW1000 is operating at 6 8 Mbps or 850 kbps this programming selects the use of a user configured SFD with length configurable in the range 8 to 16 symbols In this mode the user is responsible for correctly programming the SFD sequence in Register file 0x21 User defined SFD sequence 110...

Page 147: ...Register 0x27 04 DRX_TUNE1a 1 16 MHz PRF 0x0087 2 64 MHz PRF 0x008D 7 2 40 4 Sub Register 0x27 06 DRX_TUNE1b ID Length octets Type Mnemonic Description 27 06 2 RW DRX_TUNE1b Digital Tuning Register 1b Register file 0x27 Digital receiver configuration sub register 0x06 is a 16 bit tuning register The value here needs to change depending on use case The values needed are given in Table 32 below Plea...

Page 148: ... PRF 0x313B006B 16 16 MHz PRF 0x331A0052 64 MHz PRF 0x333B00BE 32 16 MHz PRF 0x351A009A 64 MHz PRF 0x353B015E 64 16 MHz PRF 0x371A011D 64 MHz PRF 0x373B0296 Note This is selecting the PAC size via bits 26 25 of the values in Table 33 The PAC size should be selected depending on the expected preamble length in the receiver For details of PAC size and its role please refer to section 4 1 1 Preamble ...

Page 149: ...mble detection WARNING Please do NOT set DRX_SFDTOC to zero disabling SFD detection timeout With the SFD timeout disabled and in the event of false preamble detection the IC will remain in receive mode until commanded to do otherwise by the external microcontroller This can lead to significant reduction in battery life 7 2 40 8 Sub Register 0x27 22 DRX_RES3 ID Length octets Type Mnemonic Descripti...

Page 150: ... message and know that the response if present will come after exactly 30 ms because the responder is using delayed send to begin the response exactly 30 ms after receiving our message We can command a 30 ms delayed receive timed from our message transmission time and have DRX_PRETOC programmed to a value of 32 which is the preamble length 1024 divided by the PAC size 32 Note that the counter auto...

Page 151: ...ecovery integrator register at address 0x27 offset 0x28 This is a 21 bit number with the lower 17 bits the fractional part and the upper 4 bits as the integer portion of the number When a packet is successfully received this register can be read and converted to the frequency error in Hz using Foffset is the absolute frequency error in Hz It can be converted to a clock offset in ppm by scaling by ...

Page 152: ...iguration of the IC analog blocks It contains a number of sub registers An overview of these is given by Table 36 Each of these sub registers is separately described in the sub sections below Table 36 Register file 0x28 Analog RF configuration block overview OFFSET in Register 0x28 Mnemonic Description 0x00 RF_CONF RF Configuration Register 0x04 RF_RES1 Reserved area 1 0x0B RF_RXCTRLH Analog RX Co...

Page 153: ...e enables Write 0x5 to enable the CLK_PLL or 0x7 to enable both the CLK_PLL and RF PLL Enabling this field will be used for certain test and calibration modes where we want to force the PLLs on when there are not packets being TX d i e Continuous Wave mode LDOFEN reg 28 00 bits 20 16 Write 0x1F to force the enable to all LDO s Enabling this field will be used for certain test and calibration modes...

Page 154: ...TRLH values RX Channel 8 bit value to program to Sub Register 0x28 0B RF_RXCTRLH 1 2 3 or 5 0xD8 4 or 7 0xBC 7 2 41 4 Sub Register 0x28 0C RF_TXCTRL ID Length octets Type Mnemonic Description 28 0C 3 RW RF_TXCTRL Analog TX Control Register Register file 0x28 Analog RF configuration block sub register 0x0C is a 24 bit control register for the transmitter The value here needs to be set depending on ...

Page 155: ... optimise performance for individual part as described in section 8 2 2 Other TX adjustments to consider 7 2 41 5 Sub Register 0x28 10 RF_RES2 ID Length octets Type Mnemonic Description 28 10 16 RW RF_RES2 Reserved area 2 Register file 0x28 Analog RF configuration block sub register 0x10 is a reserved register Please take care not to write to this register as doing so may cause the DW1000 to malfu...

Page 156: ...remainder of this register is reserved 7 2 41 7 Sub Register 0x28 30 LDOTUNE ID Length octets Type Mnemonic Description 28 30 5 RW LDOTUNE Internal LDO voltage tuning parameter REG 28 30 LDOTUNE LDO voltage tuning 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LDOTUNE 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 REG 28 30 LDOTUNE LDO voltag...

Page 157: ... Table 39 Register file 0x2A Transmitter Calibration block overview OFFSET in Register 0x2A Mnemonic Description 0x00 TC_SARC Transmitter Calibration SAR control 0x03 TC_SARL Transmitter Calibration Latest SAR readings 0x06 TC_SARW Transmitter Calibration SAR readings at last Wake Up 0x08 TC_PG_CTRL Transmitter Calibration Pulse Generator Control 0x09 TC_PG_STATUS Transmitter Calibration Pulse Gen...

Page 158: ...ds REG 2A 03 TC_SARL Transmitter Calibration Latest SAR readings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAR_LTEMP SAR_LVBAT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Definition of the bit fields within Sub Register 0x2A 03 TC_SARL Field Description of fields within Sub Register 0x2A 03 TC_SARL SAR_LVBAT reg 2A 03 bits 7 0 Latest SAR reading for ...

Page 159: ...bration block sub register 0x06 is a 16 bit status register that contains the following bitmapped sub fields REG 2A 06 TC_SARW Transmitter Calibration SAR readings at last Wake Up 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAR_WTEMP SAR_WVBAT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Definition of the bit fields within Sub Register 0x2A 06 TC_SARW Field Description...

Page 160: ...is bit is self clearing PG_TMEAS reg 2A 08 bit5 2 Number of clock cycles over which to run the pulse generator cal counter These are the upper 4 MSb s of a 10 bit counter clocked by the system clock This register controls the pulse generator calibration When a calibration is complete it generates a pulse generator delay count based on the current TC_PGDELAY value The count value is then stored aut...

Page 161: ...e and calculates the TC_PGDELAY value from this This TC_PGDELAY value can then be programmed in to give the desired bandwidth More details on using these registers for bandwidth temperature compensation can be found in the following application note APS023 Part 2 7 2 43 6 Sub Register 0x2A 0B TC_PGDELAY ID Length octets Type Mnemonic Description 2A 0B 1 RW TC_PGDELAY Transmitter Calibration Pulse ...

Page 162: ...Test Mode 0x13 For more details of crystal trimming please refer to section 8 1 IC Calibration Crystal Oscillator Trim 7 2 44 Register file 0x2B Frequency synthesiser control block ID Length octets Type Mnemonic Description 0x2B FS_CTRL Frequency synthesiser control block Register map register file 0x2B is the frequency synthesiser control block Its main functionality is the generation of the carr...

Page 163: ...and TX_CHAN configuration in Register file 0x1F Channel Control The values required are given in Table 43 Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction Table 43 Sub Register 0x2B 07 FS_PLLCFG values Operating Channel 32 bit value to program to Sub Register 0x2B 07 FS_PLLCFG 1 0x09000407 2 4 0x08400508 3 0x08401009 5 7 0x0800041D 7 2 44 ...

Page 164: ...ion 7 2 44 5 Sub Register 0x2B 0E FS_XTALT ID Length octets Type Mnemonic Description 2B 0E 1 RW FS_XTALT Frequency synthesiser Crystal trim Register file 0x2B Frequency synthesiser control block sub register 0x0E is the crystal trim register This allows a fine control over the crystal oscillator to tune the DW1000 operating frequencies quite precisely For details of the use of this register pleas...

Page 165: ... remains powered up as long as power from the battery for example is supplied to the DW1000 via the VDDAON pin User configurations from SPI accessible host interface registers can be automatically saved in the AON memorywhen the DW1000 enters SLEEP or DEEPSLEEP states and automatically restored from the AON memorywhen the DW1000 wakes from sleeping Additional discussion of these modes may be found...

Page 166: ... measure of the ambient temperature around the IC and the battery voltage is measured before any significant current drain occurs which may be useful in checking battery health The resultant temperature and voltage values are available in Sub Register 0x2A 06 TC_SARW For more details of this functionality please refer to section 6 4 Measuring IC temperature and voltage ONW_RX reg 2C 00 bit 1 On Wa...

Page 167: ...LDE microcode The LDE algorithm is implemented in a microcode that is stored in a special ROM area on the DW1000 but run from a RAM area Before the LDE is run the DW1000 has to copy it from ROM to RAM The LDE algorithm is responsible for generating an accurate RX timestamp and calculating some signal quality statistics related to the received packet See Register file 0x2E Leading Edge Detection In...

Page 168: ...correctly configuring it in those two registers although SLEEP may be automatically entered under certain conditions by appropriate configurations within Register file 0x36 Power Management and System Control If the UPL_CFG is being set for a purpose other than going to sleep then needs to be explicitly cleared immediately after use as it is not self clearing DCA_READ reg 2C 02 bit 3 Direct AON me...

Page 169: ...NE1 Sub Register 0x2E 1806 LDE_CFG2 Sub Register 0x23 12 AGC_TUNE3 Sub Register 0x2E 2804 LDE_REPC Sub Register 0x26 00 GPIO_MODE Sub Register 0x36 00 PMSC_CTRL0 6 Register file 0x27 Digital receiver configuration Sub Register 0x36 04 PMSC_CTRL1 7 Sub Register 0x36 0C PMSC_SNOZT Sub Register 0x36 28 PMSC_LEDC 8 2 Only the Low 32 bits are maintained 3 All bits are maintained except for bit 0 Bit ze...

Page 170: ...ing the DCA_READ control bit in Sub Register 0x2C 02 AON_CTRL 7 2 45 4 Reading from a specified address within AON memory Figure 28 shows the procedural flow for reading from specified address in AON memory Figure 28 Flow chart for direct read of AON address Ensure that the SPI clock frequency is set 3MHz YES NO Want to do another read Write Address to access into Register 2C 04 AON_ADDR Set DCA_E...

Page 171: ... for the always on block The fields of this register are interpreted inside the AON block which can only happen after these are loaded into the AON block via the UPL_CFG command in Sub Register 0x2C 02 AON_CTRL The AON_CFG0 register contains the following fields REG 2C 06 AON_CFG0 AON Configuration Register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLE...

Page 172: ...or frequency to set an LP clock frequency This LP clock and LPCLKDIVA functionality is only enabled when the LPDIV_EN configuration bit is set to 1 The raw 38 4 MHz XTAL oscillator frequency input to the LP clock divider is pre divided by 2 to give a 19 2 MHz internal clock called XTI The LPCLKDIVA field is 11 bits allowing divisors up to 2047 or LP clock frequencies down to 9 4 kHz An LPCLKDIVA v...

Page 173: ... AON_CFG1 to 0 b Set UPL_CFG in AON_CTRL to 1 to apply this to the AON block c Program the new value of SLEEP_TIM in AON_CFG0 d Set SLEEP_CEN to 1 e Set UPL_CFG to 1 to apply the new sleep time and enable the counter in the AON SMXX reg 2C 0A bit 1 This bit needs to be set to 0 for correct operation in the SLEEP state within the DW1000 By default this bit is set to 1 The host system should set thi...

Page 174: ...e SYSCLKS configuration back to 0 The operating frequency of the ring oscillator is given by 19 2 MHz divided by the period counter value reg 2C 0A bits 15 3 Reserved bits 7 2 46 Register file 0x2D OTP Memory Interface ID Length octets Type Mnemonic Description 0x2D OTP_IF One Time Programmable Memory Interface Register map register file 0x2D is the OTP memory interface This allows read access to ...

Page 175: ...2D OTP Memory Interface sub register 0x04 is a 16 bit register used to select the address within the OTP memory block that is being accessed for read or write this OTP memory interface The OTP_ADDR register contains the following fields REG 2D 04 OTP_ADDR OTP Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTPADDR 0 0 0 0 0 0 0 0 0 0 0 The fields of th...

Page 176: ... available in the OTP_RDAT register This bit will automatically clear when the read operation is done For details of the OTP memory map and the procedures to read and write OTP memory please refer to section 6 3 Using the on chip OTP memory OTPMRWR reg 2D 06 bit 3 OTP mode register write This bit should be set to 1 then cleared when applying a new mode to the OTP This bit is used to configure the ...

Page 177: ...EP to receive a frame if the ONW_LLDE bit in Sub Register 0x2C 00 AON_WCFG has been configured to 1 then the LDE load will be done automatically as part of exiting the sleep state 7 2 46 4 Sub Register 0x2D 08 OTP_STAT ID Length octets Type Mnemonic Description 2D 08 2 RW OTP_STAT OTP Status Register file 0x2D OTP Memory Interface sub register 0x08 is a 16 bit register used to give status informat...

Page 178: ... Register Read Data Register file 0x2D OTP Memory Interface sub register 0x0E is a 32 bit register The data value stored in the OTP SR 0x400 location will appear here after power up For details of the OTP memory map and the procedures to read OTP memory please refer to section 6 3 Using the on chip OTP memory 7 2 46 7 Sub Register 0x2D 12 OTP_SF ID Length octets Type Mnemonic Description 2D 12 1 R...

Page 179: ...the host system designer depending on system characteristics Table 48 below lists and defines these operating parameter sets indicating their recommended usages Table 48 Receiver operating parameter sets Set Description 10 Default This is the default operating parameter set This parameter set is designed to work at all data rates and can tolerate a total clock offset between the transmit and recei...

Page 180: ... in Register file 0x25 Accumulator CIR memory to find the first path and calculate the RX timestamp written to Register file 0x15 Receive Time Stamp and the diagnostic information written into Register file 0x12 Rx Frame Quality Information The LDE interface contains a number of sub registers An overview of these sub registers is given by Table 49 and each is then separately described in the sub s...

Page 181: ...able compromise performance level between falsely triggering on noise peaks and missing real attenuated non line of sight first paths More recently an NTM value of 13 has been used in our device driver software to give more accuracy in close up LOS conditions Where NLOS performance is more important to the application the default NTM value of 12 might be a better choice Refer to the application no...

Page 182: ...HR at the antenna and the time the RMARKER is detected and time stamped by the internal digital RX circuitry The units here are the same as those used for system time and time stamps i e 499 2 MHz 128 so the least significant bit about 15 65 picoseconds The value programmed in this LDE_RXANTD register value is subtracted by the LDE algorithm from the raw timestamp RX_RAWST to by the LDE algorithm ...

Page 183: ... of the channel impulse response appear repeatedly throughout the accumulator span The magnitude of this effect is dependent on the clock offset and on the preamble code being employed To avoid the LDE erroneously seeing one of these replica signals as the leading edge the threshold used for detecting the first path is artificially raised by a factor depending on the measured clock offset For opti...

Page 184: ...n overview of these is given by Table 52 Each of these sub registers is separately described in the sub sections below Table 52 Register file 0x2F Digital Diagnostics Interface overview OFFSET in Register 0x2F Mnemonic Description 0x00 EVC_CTRL Event Counter Control 0x04 EVC_PHE PHR Error Counter 0x06 EVC_RSE RSD Error Counter 0x08 EVC_FCG Frame Check Sequence Good Counter 0x0A EVC_FCE Frame Check...

Page 185: ...ate When EVC_EN bit is set to 1 it enables event counting A number of sub registers of Register file 0x2F Digital Diagnostics Interface contain counters of various system events see below for the detailed description of the parameters counted If the host system has no interest in these event counters then a small amount of power is saved by not enabling event counting EVC_CLR reg 2F 00 bit 1 Event...

Page 186: ...F Digital Diagnostics Interface sub register 0x06 is the RSD Error event counter REG 2F 06 EVC_RSE RSD Error Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVC_RSE 0 The fields of the EVC_RSE register are described below Field Description of fields within Sub Register 0x2F 06 RSD Error Counter EVC_RSE reg 2F 06 bits 11 0 Reed Solomon decoder Frame Syn...

Page 187: ...FCE Frame Check Sequence Error Counter Register file 0x2F Digital Diagnostics Interface sub register 0x0A is the FCS Error event counter REG 2F 0A EVC_FCE FCS Error Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVC_FCE 0 The bits of the EVC_FCE register are described below Field Description of fields within Sub Register 0x2F 0A FCS Error Counter EVC_...

Page 188: ...r Register file 0x2F Digital Diagnostics Interface sub register 0x0E is the RX Overrun Error counter REG 2F 0E EVC_OVR RX Overrun Error Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVC_OVR 0 The bits of the EVC_OVR register are described below Field Description of fields within Sub Register 0x2F 0C Frame Filter Rejection Counter EVC_OVR reg 2F 0E bi...

Page 189: ...nt Counter Register file 0x2F Digital Diagnostics Interface sub register 0x12 is the Preamble Timeout Event Counter REG 2F 12 EVC_PTO Preamble Detection Timeout Event Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVC_PTO 0 The bits of the EVC_PTO register are described below Field Description of fields within Sub Register 0x2F 12 Preamble Detection T...

Page 190: ... EVC_TXFS TX Frame Sent Counter Register file 0x2F Digital Diagnostics Interface sub register 0x16 is the TX Frame Sent Counter REG 2F 16 EVC_TXFS TX Frame Sent Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVC_TXFS 0 The bits of the EVC_TXFS register are described below Field Description of fields within Sub Register 0x2F 16 TX Frame Sent Counter EV...

Page 191: ...ption 2F 1A 2 RO EVC_TPW Transmitter Power Up Warning Counter Register file 0x2F Digital Diagnostics Interface sub register 0x1A is the TX Power Up Warning Counter REG 2F 1A EVC_TPW Transmitter Power Up Warning Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVC_TPW 0 The bits of the EVC_TPW register are described below Field Description of fields with...

Page 192: ...est mode is provided to help support regulatory approvals spectral testing When the TX_PSTM bit is set it enables a repeating transmission of the data from the TX_BUFFER To use this test mode the operating channel preamble code data length offset etc should all be set up as if for a normal transmission The start to start delay between frames is programmed in the DX_TIME register This is a special ...

Page 193: ...able 53 Register file 0x36 Power Management and System Control overview OFFSET in Register 0x36 Mnemonic Description 0x00 PMSC_CTRL0 PMSC Control Register 0 0x04 PMSC_CTRL1 PMSC Control Register 1 0x08 PMSC_RES1 PMSC reserved area 1 0x0C PMSC_SNOZT PMSC Snooze Time Register 0x10 PMSC_RES2 PMSC reserved area 2 0x26 PMSC_TXFSEQ PMSC fine grain TX sequencing control 0x28 PMSC_LEDC PMSC LED Control Re...

Page 194: ... the 19 2 MHz XTI clock for manual access to OTP Memory RXCLKS reg 36 00 bits 3 2 Receiver Clock Selection This selects the source of clock for the DW1000 receiver Allowed values are 00 Auto The RX clock will be disabled until it is required for an RX operation at which time it will be enabled to use the 125 MHz PLL clock 01 Force RX clock enable and sourced clock from the 19 2 MHz XTI clock 10 Fo...

Page 195: ... to take the GPIO port out of its reset state GPRN reg 36 00 bit 17 GPIO reset NOT active low In order to use the GPIO port lines GPRN bit must be set to 1 to take the GPIO port out of its reset state The GPCE enable bit above must also be set to 1 to enable the clock into the GPIO block GPDCE reg 36 00 bit 18 GPIO De bounce Clock Enable The DW1000 GPIO port includes a de bounce functionality that...

Page 196: ...4 is a 32 bit control register The PMSC_CTRL1 register contains the following sub fields REG 36 04 PMSC_CTRL1 PMSC Control Register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KHZCLKDIV LDERUNE PLLSYN SNOZR SNOZE ARXSLP ATXSLP PKTSEQ ARX2INIT 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 The fields of the PMSC_CTRL1 register identified ...

Page 197: ...specified by the SNOZ_TIM field of Sub Register 0x36 0C PMSC_SNOZT Snoozing is more precisely timed than sleeping but has a higher power drain than sleeping This is used to implement the Low Power Listening scheme see section 4 4 Low Power Listening for more details SNOZR reg 36 04 bit 14 Snooze Repeat The SNOZR bit is set to allow the snooze timer to repeat indefinitely SNOOZE RX SNOOZE RX etc PL...

Page 198: ...0 1 0 0 0 0 0 0 The fields of the PMSC_CTRL1 register identified above are individually described below Field Description of fields within Sub Register 0x36 0C PMSC_SNOZT SNOZ_TIM reg 36 0C bits 7 0 Snooze Time Period These bits are the upper 8 bits of a 17 bit timer that defines the snooze period in units of the 19 2 MHz XTI internal clock The default value 0x40 or decimal 64 gives a period of 64...

Page 199: ...ain test and calibration modes Continuous Wave transmission To enable fine grain power sequencing the default value of 0x0B74 should be written back to this register Note that TX fine grain power sequencing must be disabled if an external power amplifier is being used with the DW1000 7 2 50 7 Sub Register 0x36 28 PMSC_LEDC ID Length octets Type Mnemonic Description 36 28 4 RW PMSC_LEDC PMSC LED Co...

Page 200: ...NKEN reg 36 28 bit 8 Blink Enable When this bit is set to 1 the LED blink feature is enabled Because the LED blink counter uses the low frequency KHZCLK timer this timer must be enabled as per Sub Register 0x36 00 PMSC_CTRL0 and configured as per Sub Register 0x36 04 PMSC_CTRL1 BLNKNOW reg 36 28 bits 19 16 Manually triggers an LED blink There is one trigger bit per LED IO 7 2 51 Register files 0x3...

Page 201: ...s may need to be changed if there are large variations in the ambient temperature e g moving from a warm area into a cold store or if there are significant changes in battery voltage supply In such circumstances in order to optimise the DW1000 performance the host system software can monitor the voltage and temperature using DW1000 and adjust configuration accordingly Elements of the DW1000 that m...

Page 202: ...arge a range of programming as possible the external loading capacitors should be chosen during the board design phase such that on average tested on a number of boards the crystal trim register setting is set close to mid range which is a 5 bit decimal value of 15or 0x0F Test Setup Reset the device so that it is in a known state before initiating the test procedure Configure the transmitter as de...

Page 203: ... the OTP memory see section 6 3 2 Programming a value into OTP memory for details of how to program OTP memory and recommended memory locations In DW1000 applications using crystal trimming the calibrated crystal trim value should be read by the application from OTP memory as part of setup and programmed into the Sub Register 0x2B 0E FS_XTALT This register is preserved in the AON memory as long as...

Page 204: ... 1 1 Calibration Manual TX Power Control Test Setup Reset the device so that it is in a known state before initiating the test procedure Configure the transmitter as described in the following steps Table 54 and monitor the RF output on a spectrum analyser Table 54 Register accesses required for transmitter configuration procedure Step Number Instruction Register Address Data Length Bytes Data Wri...

Page 205: ... set up as follows Resolution Bandwidth 1 MHz Video Bandwidth 1 MHz Span 2 GHz Sweep time 2 seconds Detector rms Average time per point on spectrum analyser scan 1 ms In order to easily view the transmit spectrum the device is set into Transmit Power Spectrum Test Mode by setting the TX_PSTM field of Sub Register 0x2F 24 Digital Diagnostics Test Mode Control A suitable value for the repeat frame i...

Page 206: ...or details of how to program OTP memory and recommended memory locations In DW1000 applications using transmit power calibration the calibrated TX_POWER value should be read by the application from OTP memory as part of setup and programmed into Register file 0x1E Transmit Power Control This register is preserved in the AON memory as long as the IC is powered This facilitates the use of this value...

Page 207: ...e antenna and the internal digital timestamp of the RMARKER at the start of the PHR see 4 1 6 RX Message timestamp inside the DW1000 Figure 30 Transmit and Receive Antenna Delay 8 3 1 Calibration Method To achieve the highest accuracy during calibration it is recommended that antenna delay is calibrated with the receiver power input at the following levels Table 55 Recommended RX power level for a...

Page 208: ...the OTP memory in the locations for both TX Antenna Delay and RX Antenna Delay see section 6 3 2 Programming a value into OTP memory for details of how to program OTP memory and recommended memory locations Note In many systems where all devices have the same transmitter and receiver antenna delays it is unnecessary to calibrate the transmitter antenna delay The transmitter antenna delay may be se...

Page 209: ...rum is within the regional regulations The IEEE 802 15 4 standard UWB PHY defines a number of channels from 0 to 10 GHz some with same centre frequency and different bandwidths e g channel 2 and channel 4 both have 3993 6 MHz centre frequency but have bandwidths of 499 2 and 1331 2 MHz respectively Table 61 in section 10 5 UWB channels and preamble codes lists the channels supported by the DW1000 ...

Page 210: ...e two choices of mean pulse repetition frequency PRF within the DW1000 These are 16 MHz PRF or 64 MHz PRF The 16 and 64 are nominal since the actual frequencies are related to the 499 2 MHz basic time unit used and differ slightly between preamble and payload parts of the frame The higher PRF gives more accuracy on the first path timestamp and perhaps slightly improved operating range however this...

Page 211: ...o as the packet is physically long the blinks in such a long range system consume more power For a high update rate or a high density of tags the highest data rate and shortest preamble length is best This means range is lower so more infrastructure anchor nodes are needed but the shorter blink packet duration means lower power consumption for transmissions so for the same update frequency the bat...

Page 212: ... which the tag must lie The tag s 3D location is yielded by the intersection of the spheres resulting from TOF measurements to the four anchors In time difference of arrival TDOA location the mobile tag blinks periodically and the blink message is received by the anchor nodes in its vicinity When the anchor nodes have synchronised clocks so that the arrival time of the blink message at all nodes c...

Page 213: ...ortant to ensure a reasonable battery life it will be necessary to include schemes to reduce the time spent listening Table 59 lists and briefly describes some techniques that can save power in receiving Table 59 Techniques to save power in receiving Name Description Low Power Listening This is a technique based on the DW1000 preamble sampling function The IC can sniff the air for a short period l...

Page 214: ...tening in a slot needs only continue for as long as necessary to confirm that no message is being sent this time The beacon period and resulting frequency of listening is a trade off between power consumption and system responsiveness Sniff mode This technique involves searching for preamble with a duty cycle of listening less than 100 of the time e g 50 of the time or 25 of the time this reduces ...

Page 215: ...gy During the PHR and Data parts of the frame information bits are signalled by the position of the burst in a modulation scheme termed burst position modulation BPM Figure 32 BPM BPSK data and PHR modulation Each data bit passes through a convolution encoder to generate a parity bit used to set the phase of the burst as either positive or negative this component of the modulation is termed binary...

Page 216: ...rate is just over 120 kbps The DW1000 supports 110 kbps 850 kbps and 6 8 Mbps data rates but does not support the 27 Mbps data rate 10 3 Synchronisation header modulation scheme The Synchronisation Header SHR consists of the preamble sequence and the SFD start of frame delimiter In contrast to the BPM BPSK modulation used for the PHR and data the synchronisation header is made up of single pulses ...

Page 217: ...very deterministic in terms of symbol times and it is this in conjunction with determining the first arriving ray within that symbol time that allows the accurate time stamping needed for precision RTLS applications The standard specifies the SFD which consists of the preamble symbols either not sent or sent as normal or sent inverted i e positive and negative pulses reversed in a defined pattern ...

Page 218: ...e gives what the standard terms a complex channel The DW1000 does not physically impose the channel code selection so it is up to the software to select the appropriate preamble code for the selected operating channel The standard notes that wideband channels may also employ the codes allocated to the narrower 499 2 MHz bandwidth channels if inter channel communication is desired Table 61 DW1000 s...

Page 219: ... preamble codes for the ranging exchange and perhaps a different one for each direction of communication The idea is to make it more difficult to eavesdrop or spoof by randomly changing the DPS preamble codes in a mutually agreed sequence only known to the valid participants This is supported by the DW1000 where at 64 MHz PRF the preamble codes additionally available for DPS are 13 14 15 16 21 22 ...

Page 220: ...ing the DW1000 s non standard long frame mode see section 3 4 Extended Length Data Frames The general structure of a MAC message consists of a header that identifies the frame followed by a variable length possibly zero payload typically from the upper layers but sometimes as in the case of MAC command frames generated within the MAC itself and finally ended by the MAC footer which is the FCS Fram...

Page 221: ... some of the reserved types have since been allocated within the IEEE 802 15 Working Group for special applications The DW1000 provides only minimal support for the new frame types by allowing their acceptance to be enabled within the frame filtering function Please refer to section 5 2 Frame filtering for details If these new frames are enabled then the host system will need to parse the received...

Page 222: ...ftware is responsible for forming the TX frame and setting the acknowledgement request field appropriately If the DW1000 s Automatic Acknowledgementfeature is not being employed then the host software should respond appropriately to the receipt of frames with the acknowledgement request bit set 11 2 5 PAN ID compression field The PAN ID compression bit specifies whether the MAC frame contains only...

Page 223: ... addressing mode field The source addressing mode field 2 bits specifies whether the frame contains a source address and if so the size of the address field Table 64 below summarises the options for source addressing mode For additional information on the addressing modes please refer to the standard 1 Table 64 Source addressing mode field values Source addressing mode FC bits 15 14 Meaning 0 0 No...

Page 224: ...s complying with IEEE 802 15 4 2011 to validate and accept only those with destination address that is the broadcast address or matches the IC address information configured in Register file 0x01 Extended Unique Identifier and Register file 0x03 PAN Identifier and Short Address The DW1000 can also optionally respond to the acknowledgement request bit set in the frame control field of correctly add...

Page 225: ...nse sent back to the original node Figure 36 Single sided Two way ranging The operation of SS TWR is as shown in Figure 36 where device A initiates the exchange and device B responds to complete the exchange and each device precisely timestamps the transmission and reception times of the message frames and so can calculate times Tround and Treply by simple subtraction And the resultant time of fli...

Page 226: ...nation for particular use cases where tight tolerance clocks are used and the communication range is relatively short Table 66 Typical clock induced error in SS TWR time of flight estimation using actual IEEE80 15 4 2011 UWB frame lengths clock error Treply 2 ppm 5 ppm 10 ppm 20 ppm 40 ppm 211 µs total 6 81 Mbps 64 Symbol Preamble 96 µs response delay 0 2 ns 0 5 ns 1 1 ns 2 1 ns 4 2 ns 275 µs tota...

Page 227: ...d round trip measurement to which device A responds completing the full DS TWR exchange Each device precisely timestamps the transmission and reception times of the messages 12 3 2 Using three messages The four messages of DS TWR shown in Figure 37 can be reduced to three messages by using the reply of the first round trip measurement as the initiator of the second round trip measurement This is s...

Page 228: ... of the same response time at each device At these error levels the precision of determining the arrival time of the message is actually the more significant source of error Advantages Drawbacks Reply times need not be the same gives great flexibility in the design of use cases and application scenarios Requires multiplication and division operations Error in the calculated time of flight is minim...

Page 229: ...3t and so on until all tags have responded Finally the anchor closes off the round with a final packet P3 Each tag can now calculate its distance from the anchor after a sequence of just 7 messages If the anchor had used symmetric S TWR it would be forced to have the same delay for each tag interaction and a minimum of 3 messages per tag or 15 messages would be required In the asymmetric case the ...

Page 230: ...nd2A Treply1A Treply2A Tround1A Tround2A Treply1A Treply2A TpropA Tround1B Tround2B Treply1B Treply2B Tround1B Tround2B Treply1B Treply2B TpropB Tround1C Tround2C Treply1C Treply2C Tround1C Tround2C Treply1C Treply2C TpropC Poll Poll Poll Poll RespA RespA RespB RespC RespB RespC Final Final Final Final The Final message communicates the tag s Tround and Treply times to the anchors which each calcu...

Page 231: ...DW1000 User Manual Decawave Ltd 2017 Version 2 12 Page 231 of 242 ...

Page 232: ...a need to send an additional message to communicate the results which could be 1 per distance measurement or just 1 per node containing all the results which that node calculated This is then a total of 35 to 40 messages in the 5 node example case With the asymmetric ranging scheme the ranging exchanges can be combined and completed with just two transmissions per node i e 10 messages in the case ...

Page 233: ...sponse The impulse response of the communications channel between transmitter and receiver as detected by DW1000 for the most recently received frame DPS dynamic preamble select Anti spoofing mechanism to allow IEEE 802 15 4 devices to move their long preamble codes to codes that are different from those in normal use see 233 1 ESD electrostatic discharge A sudden flow of electrical current betwee...

Page 234: ...ad and defines various characteristics of that payload required by the receiver for successful reception PHY physical layer Defined in the context of the OSI 7 layer model for communications systems in general and the IEEE802 15 4 2011 UWB standard in particular the PHY layer is the lowest layer in the 7 layermodel and defines the physical interface to the communications medium PLL phase locked lo...

Page 235: ...dard The first portion of an IEEE802 15 4 2011 UWB frame containing the preamble and SFD SPI serial peripheral interface An industry accepted method for interfacing between IC s using a synchronous serial scheme first introduced by Motorola TDOA time difference of arrival Method of deriving information on the location of a transmitter The time of arrival of a transmission at two physically differe...

Page 236: ...ly 2014 Scheduled update 2 03 31 st December 2014 Scheduled update 2 04 31 st March 2015 Scheduled update 2 05 30 th June 2015 Scheduled update 2 06 17 th November 2015 Scheduled update 2 07 31 st December 2015 Scheduled update 2 08 31 st March 2016 Scheduled update 2 09 30 th June 2016 Scheduled update 2 10 30 th September 2016 Scheduled update 16 Change Log Revision v2 03 Page Change Description...

Page 237: ... of CLKPLL_LL bit 106 Modification to Table 26 transmit power octet 119 Inclusion of PLLLDT bit description 143 Modification to description of CPLLLOCK 149 Modification to Table 41 default values for FS_PLLTUNE for channels 5 7 167 Modification of NSTD to NTM 217 Addition of v2 04 to table 64 217 Inclusion of this table Revision v2 05 Page Change Description All Update of version number to v2 05 A...

Page 238: ...phical changes and formatting corrections 62 TX_BUFFER register type corrected to write only 62 RX_BUFFER register type corrected to write only 76 TX_BUFFER register type changed to write only 92 93 RXPACC field of RX_FINFO updated to describe adjustments that can be made to the count to calculate more accurate receive signal power as used in calculations in section 4 7 96 RX_BUFFER register type ...

Page 239: ... v2 09 Page Change Description All Update of version number to v2 09 All Various typographical changes and formatting corrections 16 Update to description of INIT state 34 Correction to receiver errors for which a receiver reset is required 41 Addition of actions required to correctly read a frame received during low power listening 42 Correction to operation of SNOZ_TIM 52 Inclusion of section on...

Page 240: ... corrections 53 Added Sect 5 3 6 ACK corruption text added 77 96 Amend TX and RX_Buffer descriptions 80 Updated description on TXSTRT bit 92 R report added to RXPF in Register REG 10 00 RX_FINFO RX Frame Information to match the resume table 95 Addition of prohibition of writing to receive buffer 114 Modification to Table 21 and addition of new Table 22 Renumbering of all subsequent tables 146 Cha...

Page 241: ...on of VDDPA1 and VDDPA2 if using Tx gain setting 000 128 Note added to point out that GPIO clocks have to be on to use GPIO lines 132 Sec 7 2 39 3 GDM6 is declared as bit 15 but it is bit 14 133 Sec 7 2 39 4 GOP2 should refer to GPIO2 and GOP3 should refer to GPIO3 140 Changed the sentence to The bits of the GPIO_RAW register identified above are individually described below 157 PG_TMEAS changed t...

Page 242: ...y of parts The resulting silicon has a wide range of standards based applications for both Real Time Location Systems RTLS and Ultra Low Power Wireless Transceivers in areas as diverse as manufacturing healthcare lighting security transport and inventory and supply chain management For further information on this or any other Decawave product contact a sales representative as follows Decawave Ltd ...

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