DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 87 of 242
Field
Description of fields within Register file: 0x0F – System Event Status Register
TXPRS
reg:0F:00
bit:5
Transmit Preamble Sent. This event status bit is set at the end of preamble when SFD sending
begins. The TXPRS bit is automatically cleared at the next transmitter enable. It can also be
cleared explicitly by writing a 1 to it.
TXPHS
reg:0F:00
bit:6
Transmit PHY Header Sent. This event status bit is set when the PHR has been transmitted.
This marks the start of sending the data part of the frame (assuming the frame length is non-
zero) at the configured transmit data rate. The TXPHS bit is automatically cleared at the next
transmitter enable. It can also be cleared explicitly by writing a 1 to it.
TXFRS
reg:0F:00
bit:7
Transmit Frame Sent. This event status bit is set at the end of sending the data part of the
frame. It is expected that this will be used as the main “Transmit Done” (interrupt) event
signalling the completion of frame transmission. (In the case where frame length is zero the
TXFRS bit is set soon after the TXPHS event flag). The TXFRS bit is automatically cleared at the
next transmitter enable. It can also be cleared explicitly by writing a 1 to it.
RXPRD
reg:0F:00
bit:8
Receiver Preamble Detected status. This event status bit is set to indicate that the receiver has
detected (and confirmed) the presence of the preamble sequence. Preamble reception
continues after RXPRD has been set until the SFD is detected as signalled by the RXSFDD event
status bit or an SFD timeout occurs as signalled by the RXSFDTO event status bit. Section 4
gives details of the frame reception process. The RXPRD bit can be cleared
explicitly by writing a 1 to it. It is also automatically cleared by the next receiver enable,
including those caused by the RXAUTR auto-re-enable.
RXSFDD
reg:0F:00
bit:9
Receiver SFD Detected. This event status bit is set to indicate that the receiver has detected
the SFD sequence and is moving on to decode the PHR. Section 4
details of the frame reception process. The RXSFDD bit can be cleared explicitly by writing a 1
to it. It is also automatically cleared by the next receiver enable, including those caused by the
RXAUTR auto-re-enable.
LDEDONE
reg:0F:00
bit:10
LDE processing done. This event status bit is set to indicate the completion of the leading edge
detection and other adjustments of the receive timestamp information. The resultant
adjusted message RX timestamp is then available in
Register file: 0x15 – Receive Time Stamp
The detection of SFD as reported by the RXSFDD event status bit marks the end of the SFD and
the start of the PHR, which also marks the RMARKER whose arrival at the antenna is the event
that defines the frame arrival timestamp. To accurately determine this timestamp the
DW1000 employs an internal algorithm to adjust the RMARKER receive time. Among other
functions this performs a leading edge detection search on the channel impulse response and
subtracts the receive antenna delay as programmed in
Sub-Register 0x2E:1804 – LDE_RXANTD
For more information on the LDE and the process on message time-stamping see section
. The LDEDONE event status flag bit is included in the RX double-
buffered swinging-set. It is automatically cleared by the RX enable. It can also be cleared
explicitly by writing a 1 to it.
RXPHD
reg:0F:00
bit:11
Receiver PHY Header Detect. This event status bit is set to indicate that the receiver has
completed the decoding of the PHR. Section 4
reception process. The RXPHD bit can be cleared explicitly by writing a 1 to it. It is also
automatically cleared by the next receiver enable, including those caused by the RXAUTR auto-
re-enable.
