DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 194 of 242
REG:36:00 – PMSC_CTRL0 – PMSC Control Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTRESET - - - -
KHZCLK
EN
- - -
GP
D
RN
GP
D
CE
GP
RN
GP
CE
AMCE
- - - -
ADCCE
- - -
FA
CE
TX
CL
KS
RX
CL
KS
SYSC
LKS
1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
The fields of the PMSC_CTRL0 register identified above are individually described below:
Field
Description of fields within Sub-Register 0x36:00 – PMSC_CTRL0
-
Bits marked ‘-’ are reserved and should be preserved at their reset value.
SYSCLKS
reg:36:00
bits:1,0
System Clock Selection. This selects the source of clock for DW1000 system clock. Allowed
values are:
00: Auto – The system clock will run off the 19.2 MHz XTI clock until the PLL is calibrated and
locked, then it will switch over the 125 MHz PLL clock.
01: Force system clock to be the 19.2 MHz XTI clock.
10: Force system clock to the 125 MHz PLL clock. (If this clock is not present the DW1000 will
essentially lock up with further SPI communications impossible. In this case an external
reset will be needed to recover).
11: Reserved.
This control is used for certain procedures, e.g. to set system clock to be the 19.2 MHz XTI
clock for manual access to OTP Memory.
RXCLKS
reg:36:00
bits:3,2
Receiver Clock Selection. This selects the source of clock for the DW1000 receiver. Allowed
values are:
00: Auto – The RX clock will be disabled until it is required for an RX operation, at which time
it will be enabled to use the 125 MHz PLL clock.
01: Force RX clock enable and sourced clock from the 19.2 MHz XTI clock
10: Force RX clock enable and sourced from the 125 MHz PLL clock. (NB: ensure PLL clock is
present).
11: Force RX clock off.
This control is used for certain procedures, e.g. after a receive operation, if the host system
wants to read the Channel Impulse Response Estimate (CIRE) for diagnostic purposes then, the
receive clock needs to be present to access the accumulator memory.
TXCLKS
reg:36:00
bits:5,4
Transmitter Clock Selection. This selects the source of clock for the DW1000 transmitter.
Allowed values are:
00: Auto – The TX clock will be disabled until it is required for a TX operation, at which time it
will be enabled to use the 125 MHz PLL clock.
01: Force TX clock enable and sourced clock from the 19.2 MHz XTI clock
10: Force TX clock enable and sourced from the 125 MHz PLL clock. (NB: ensure PLL clock is
present).
11: Force TX clock off.
This control is used for certain procedures, e.g. when setting up the continuous transmission
mode that is used during power output calibration and regulatory testing.
