DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 38 of 242
Set up RX channel and other
parameters as required
Read SYS_STATUS reg:0F to
checking that HSRBP == ICRBP
HSRBP == ICRBP ?
Issue the HRBPT command in
reg:0x0D
Set RXENAB bit = 1, in reg:0D,
to enable the receiver
Set DIS_DRXB bit = 0 in reg:04
to Enable double buffering
YES
NO
Await frame arrival, as signalled
by the RXFCG event flag (IRQ)
Read the data in RX_BUFFER
reg:11.
Read other registers of interest
e.g. RX_FINFO reg:10, RX
timestamp in reg:15 and perhaps
frame quality reg:12.
RXOVRR==1
Issue the HRBPT to reg:0D to
signal finished with this buffer
and moving on to other of pair.
NO
YES
Set RXAUTR bit = 1 in reg:04
to enable RX auto-re-enable
Clear RX event flags in
SYS_STATUS reg:0F; bits FCE,
FCG, DFR, LDE_DONE
Frames must be discarded (do
not read frames) due to
corrupted registers and TRXOFF
command issued.
Receiver must be reset to exit
errored state.
Unmask Double buffered status
bits; FCE, FCG, DFR, LDE_DONE
Mask Double buffered status
bits; FCE, FCG, DFR, LDE_DONE
to prevent glitch when cleared
Rx more frames?
YES
HSRBP == ICRBP ?
YES
NO
Issue TRXOFF command and
clear double buffered status bits
to prevent spurious RX interrupts
NO
YES
NO
Rx more frames?
EXIT
Figure 14: Flow chart for using double RX buffering
In Figure 14 the section marked by the dashed black line can be omitted if the host system is able to service
the buffers with sufficient speed so that both buffers are never full at the same time. If this can be
guaranteed then an overrun (RXOVRR) can never occur and so cannot corrupt good frames, see section
4.3.5. In this case, buffer handling is simplified.
4.3.4 TRXOFF when using Double Buffering
To prevent spurious interrupts and for predictable behavior, TXRXOFF should be applied as shown below.
The double-buffered status bits should be cleared after the TRXOFF is applied and the interrupts on double-
buffered status bits should be masked while the bits are cleared.
