D-Link DGE-560SX User Guide
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0x08 0xFFFF 0x0000
0x09 0x0000 0xFF00
0x0A 0x7C00 0x0000
0x10 0x0000 0xFFBF
0x11 0x7C00 0x0000
0x19 0x7C00 0x0000
0x1E 0x0000 0xFFFF
0x1F 0x0000 0xFFFF
C5
VPD
The VPD test first saves the contents of the vital product data
(VPD) memory before performing the test. The test then writes 1
of the 5 test data patterns (0xFF, 0xAA, 0x55, increment data, or
decrement data) into VPD memory. By default, an incremental
data pattern is used. The test writes and reads back the data for
the entire test range, and then restores the original contents of
the VPD memory.
C6
ASF Hardware
Reset Test.
This test sets the reset bit and polls for self-clearing
bits. This test verifies the reset value of the registers.
Event Mapping Test.
This test sets the SMB_ATTN bit. By
changing ASF_ATTN_ LOC bits, the test verifies the mapping bits
in TX_CPU or RX_CPU event bits.
Counter Test
Clears WG_TO, HB_TO, PA_TO, PL_TO, RT_TO bits (by
setting the bits) and ensures that the bits clear.
Clears the timestamp counter. Writes a 1 to each of the
PL, PA, HB, WG, RT counters. Sets the TSC_EN bit.
Polls each PA_TO bit and counts up to 50. Checks if the
PL_TO bit is set at the end of the count to 50. Continues
to count up to 200. Checks if all other TO bits are set and
verifies if the timestamp counter is incremented.
C7
Expansion
ROM
This test tests the ability to enable, disable, and access the
expansion read-only memory (ROM) on the adapter.
C8
CPU Fetch
This test tests the PCU instruction fetch logic 100 times.
Group D: Driver Associated Tests
