MB95310L/370L Series
Document Number: 002-07519 Rev. *A
Page 51 of 80
(Continued)
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
F
CH
(main oscillation)
F
CRH
(Main CR clock)
F
CL
(sub-oscillation)
F
CRL
(Sub-CR clock)
SCLK
(source clock)
MCLK
(machine clock)
Clock mode select bits
(SYCC2: RCS1, RCS0)
Machine clock divide ratio select bits
(SYCC: DIV1, DIV0)
Division
circuit
×
×
×
×
1
1/4
1/8
1/16
Divided
by 2
Divided
by 2
Divided
by 2
Main PLL
×
×
×
2
2.5
4
• Schematic diagram of the clock generation block
