Cypress MB95310L Series, Manual

Page: 37 / 80

MB95310L/370L Series
Document Number: 002-07519 Rev. *A Page 37 of 80
(Continued)
Address
Register
abbreviation
Register name R/W Initial value
0060
H
IBCR00 I
2
C bus control register 0 R/W 00000001
B
0061
H
IBCR10 I
2
C bus control register 1 R/W 00000000
B
0062
H
IBCR0 I
2
C bus status register R 00000000
B
0063
H
IDDR0 I
2
C data register R/W 00000000
B
0064
H
IAAR0 I
2
C address register R/W 00000000
B
0065
H
ICCR0 I
2
C clock control register R/W 00000000
B
0066
H
to
006B
H
— (Disabled) — —
006C
H
ADC1 8/10-bit A/D converter control register 1 R/W 00000000
B
006D
H
ADC2 8/10-bit A/D converter control register 2 R/W 00000000
B
006E
H
ADDH 8/10-bit A/D converter data register upper R/W 00000000
B
006F
H
ADDL 8/10-bit A/D converter data register lower R/W 00000000
B
0070
H
WCSR Watch counter status register R/W 00000000
B
0071
H
FSR2 Flash memory status register 2 R/W 00000000
B
0072
H
FSR Flash memory status register R/W 000X0000
B
0073
H
SWRE0 Flash memory sector write control register 0 R/W 00000000
B
0074
H
FSR3 Flash memory status register 3 R 00000000
B
0075
H
— (Disabled) — —
0076
H
WREN Wild register address compare enable register R/W 00000000
B
0077
H
WROR Wild register data test setting register R/W 00000000
B
0078
H
— Mirror of register bank pointer (RP) and direct bank pointer (DP) — —
0079
H
ILR0 Interrupt level setting register 0 R/W 11111111
B
007A
H
ILR1 Interrupt level setting register 1 R/W 11111111
B
007B
H
ILR2 Interrupt level setting register 2 R/W 11111111
B
007C
H
ILR3 Interrupt level setting register 3 R/W 11111111
B
007D
H
ILR4 Interrupt level setting register 4 R/W 11111111
B
007E
H
ILR5 Interrupt level setting register 5 R/W 11111111
B
007F
H
— (Disabled) — —
0F80
H
WRARH0 Wild register address setting register (upper) ch. 0 R/W 00000000
B
0F81
H
WRARL0 Wild register address setting register (lower) ch. 0 R/W 00000000
B
0F82
H
WRDR0 Wild register data setting register ch. 0 R/W 00000000
B
0F83
H
WRARH1 Wild register address setting register (upper) ch. 1 R/W 00000000
B
0F84
H
WRARL1 Wild register address setting register (lower) ch. 1 R/W 00000000
B
0F85
H
WRDR1 Wild register data setting register ch. 1 R/W 00000000
B
0F86
H
WRARH2 Wild register address setting register (upper) ch. 2 R/W 00000000
B
0F87
H
WRARL2 Wild register address setting register (lower) ch. 2 R/W 00000000
B
0F88
H
WRDR2 Wild register data setting register ch. 2 R/W 00000000
B