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MB95310L/370L Series

Document Number: 002-07519 Rev. *A

Page 26 of 80

12. Block Diagram (MB95310L Series)

Flash with security function

(60/36/20 Kbyte)

RAM (2032/1008/496 bytes)

Interrupt controller

8/10-bit A/D converter

8/16-bit composite

timer ch. 0

Reset with LVD

Clock control

On-chip debug

Wild register

External interrupt

Port

MC-8FX CPU

Internal Bus

P22/TO00

P50/TO01

P51/EC0

8/16-bit composite

timer ch. 1

P42/TO11

P41/TO10

P40/EC1

P00/AN00-P03/AN03

RST

X1A

X0A

P12/DBG

P00/INT00-P07/INT07

*: 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as an event counter when the event counter operating mode is enabled.

Watch counter

UART/SIO ch. 0

UART/SIO ch. 1

P14/UCK0

P11/UO0

P10/UI0

PG0/UCK1

P94/UO1

P95/UI1

8/16bit PPG ch. 0

8/16bit PPG ch. 1

P20/PPG00

P21/PPG01

P16/PPG10

P15/PPG11

P23/SCL0

P24/SDA0

P13/ADTG

16-bit reload timer

P52/TI0

P53/TO0

LCDC

(40 SEG

4 COM)

P90/V3-P93/V0

PA0/COM0-PA3/COM3

PB0/SEG00-PB7/SEG07

PC0/SEG08-PC7/SEG15

P60/SEG16-P67/SEG23

PE0/SEG24-PE7/SEG31

P43/SEG32-P40/SEG35

P07/SEG36-P04/SEG39

Oscillator

circuit

Main PLL

oscillator

Summary of Contents for MB95310L Series

Page 1: ...n 50 kHz Max 200 kHz Timer 8 16 bit composite timer 8 16 bit PPG 16 bit reload timer Event counter Time base timer Watch prescaler UART SIO Capable of clock asynchronous UART serial data transfer and...

Page 2: ...voltage detection levels for generating interrupts Clock supervisor counter Built in clock supervisor counter function Programmable port input voltage level CMOS input level hysteresis input level Du...

Page 3: ...I O Map MB95310L Series 28 I O Map MB95370L Series 34 Interrupt Source Table 39 Electrical Characteristics 40 Absolute Maximum Ratings 40 Recommended Operating Conditions 42 DC Characteristics 43 AC...

Page 4: ...open drain 3 Time base timer Interval time 0 256 ms 8 3 s external clock frequency 4 MHz Hardware software watchdog timer Reset generation cycle Main oscillation clock at 10 MHz 105 ms Min The sub CR...

Page 5: ...le mented When the event counter function is used the 16 bit reload timer and the 8 16 bit composite timer ch 1 are unavailable 8 16 bit PPG 2 channels Each channel of the PPG can be used as 8 bit PPG...

Page 6: ...k at 10 MHz 105 ms Min The sub CR clock can be used as the source clock of the hardware watchdog timer Wild register It can be used to replace three bytes of data I2C 1 channel Master Slave sending an...

Page 7: ...of the PPG can be used as 8 bit PPG 2 channels or 16 bit PPG 1 channel Counter operating clock Eight selectable clock sources Watch counter Count clock Four selectable clock sources 125 ms 250 ms 500...

Page 8: ...um value 3 Packages And Corresponding Products O Available X Unavailable Oscillation stabilization wait time Remarks 210 2 FCRH Approx 128 s when the main CR clock is 8 MHz Oscillation stabilization w...

Page 9: ...ion on each package see Packages And Corresponding Products and Electrical Characteristics Operating voltage The operating voltage varies depending on whether the on chip debug function is used or not...

Page 10: ...9 40 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVcc SCL0 P23 TO00 P22 PPG01 P21 PPG00 P20 X0 X1 Vss SDA0 P24 PC5 SEG13 PC4 SEG12 PC3 SEG11 PC2 SEG10 PC1 SE...

Page 11: ...2 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVcc SCL0 P23 TO00 P22 PPG01 P21 PPG00 P20 X0 X1 Vss SDA0 P24 PC3 SEG11 PC2 SEG10 PC1 SEG09 PC0 SEG08 PB7 SEG07 PB6 SEG06 PB5 SEG...

Page 12: ...0 data input pin 9 P53 H General purpose I O port TO0 16 bit reload timer ch 0 output pin 10 P52 H General purpose I O port TI0 16 bit reload timer ch 0 input pin The pin can also be used as the event...

Page 13: ...9 P93 R General purpose I O port V0 LCDC drive power supply pin 30 P94 H General purpose I O port UO1 UART SIO ch 0 data output pin 31 P95 G General purpose I O port UI1 UART SIO ch 0 data input pin 3...

Page 14: ...pose I O port SEG11 LCDC SEG output pin 48 PC4 M General purpose I O port SEG12 LCDC SEG output pin 49 PC5 M General purpose I O port SEG13 LCDC SEG output pin 50 PC6 M General purpose I O port SEG14...

Page 15: ...G29 LCDC SEG output pin 66 PE6 N General purpose I O port SEG30 LCDC SEG output pin 67 PE7 M General purpose I O port SEG31 LCDC SEG output pin 68 P43 M General purpose I O port SEG32 LCDC SEG output...

Page 16: ...port INT04 External interrupt input pin SEG39 LCDC SEG output pin 76 P03 J General purpose I O port INT03 External interrupt input pin AN03 A D analog input pin 77 P02 J General purpose I O port INT0...

Page 17: ...urpose I O port ADTG A D trigger input ADTG pin TO01 8 16 bit composite timer ch 0 output pin 6 P12 C General purpose I O port DBG DBG input pin 7 P11 H General purpose I O port UO0 UART SIO ch 0 data...

Page 18: ...in 27 PA3 M General purpose I O port COM3 LCDC COM output pin 28 PB0 M General purpose I O port SEG00 LCDC SEG output pin 29 PB1 M General purpose I O port SEG01 LCDC SEG output pin 30 PB2 M General p...

Page 19: ...SEG output pin 46 P66 M General purpose I O port SEG18 LCDC SEG output pin 47 P67 M General purpose I O port SEG19 LCDC SEG output pin 48 PE0 M General purpose I O port SEG20 LCDC SEG output pin 49 P...

Page 20: ...05 External interrupt input pin SEG30 LCDC SEG output pin TO10 8 16 bit composite timer ch 1 output pin 59 P04 Q General purpose I O port INT04 External interrupt input pin SEG31 LCDC SEG output pin E...

Page 21: ...N ch open drain output Hysteresis input G CMOS output Hysteresis input CMOS input Pull up control available H CMOS output Hysteresis input Pull up control available N ch Clock input Standby control X...

Page 22: ...esis input N CMOS output LCD output Hysteresis input CMOS input N ch Standby control Hysteresis input Digital output CMOS input N ch P ch P ch R Pull up control Digital output Digital output Analog in...

Page 23: ...may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage As a rule of voltage stabilization suppress...

Page 24: ...d conform to the total output current standard always connect the VCC pin and the VSS pin to the power supply and ground outside the device In addition connect the current supply source to the VCC pin...

Page 25: ...m aims to avoid noise coupled between the oscillator pins and GPIO which may cause the main oscillator or the sub oscillator to malfunction DBG Since the DBG input pin becomes a communication pin in o...

Page 26: ...3 AN03 RST X1 X0 X1A X0A P12 DBG P00 INT00 P07 INT07 8 16 bit composite timer ch 1 and 16 bit reload timer ch 0 can be used as an event counter when the event counter operating mode is enabled Watch c...

Page 27: ...hip debug Wild register External interrupt Port Port F2MC 8FX CPU Internal Bus P22 TO00 P13 TO01 P14 EC0 8 16 bit composite timer ch 1 P05 TO10 P06 TO11 P04 EC1 P00 AN00 P03 AN03 RST X1 X0 X1A X0A P12...

Page 28: ...B95F314E F314L MB95F374E F374L Flash 4 Kbyte I O area Access prohibited RAM 1008 bytes Registers Access prohibited Extended I O area Vacant Flash 32 Kbyte Flash 4 Kbyte 0000H 0080H 0090H 0100H 0200H 0...

Page 29: ...000B 000CH WDTC Watchdog timer control register R W 00000000B 000DH SYCC2 System clock control register 2 R W XX100011B 000EH PDR2 Port 2 data register R W 00000000B 000FH DDR2 Port 2 direction regist...

Page 30: ...1 8 16 bit composite timer 11 status control register 1 ch 1 R W 00000000B 0039H T10CR1 8 16 bit composite timer 10 status control register 1 ch 1 R W 00000000B 003AH PC01 8 16 bit PPG01 control regis...

Page 31: ...R10 I2 C bus control register 1 R W 00000000B 0062H IBCR0 I2 C bus status register R 00000000B 0063H IDDR0 I2 C data register R W 00000000B 0064H IAAR0 I2 C address register R W 00000000B 0065H ICCR0...

Page 32: ...CR0 8 16 bit composite timer 01 status control register 0 ch 0 R W 00000000B 0F93H T00CR0 8 16 bit composite timer 00 status control register 0 ch 0 R W 00000000B 0F94H T01DR 8 16 bit composite timer...

Page 33: ...dedicated baud rate generator baud rate setting register ch 1 R W 00000000B 0FC2H Disabled 0FC3H AIDRL A D input disable register lower R W 00000000B 0FC4H LCDCC LCDC control register R W 00010000B 0F...

Page 34: ...ister name R W Initial value 0FEBH WDTH Watchdog timer selection ID register upper R XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register lower R XXXXXXXXB 0FEDH Disabled 0FEEH ILSR Input level s...

Page 35: ...register R W 00000000B 000DH SYCC2 System clock control register 2 R W XX100011B 000EH PDR2 Port 2 data register R W 00000000B 000FH DDR2 Port 2 direction register R W 00000000B 0010H to 0015H Disabl...

Page 36: ...r ch 0 R W 00000000B 0040H to 0047H Disabled 0048H EIC00 External interrupt circuit control register ch 0 ch 1 R W 00000000B 0049H EIC10 External interrupt circuit control register ch 2 ch 3 R W 00000...

Page 37: ...0076H WREN Wild register address compare enable register R W 00000000B 0077H WROR Wild register data test setting register R W 00000000B 0078H Mirror of register bank pointer RP and direct bank pointe...

Page 38: ...t PPG01 duty setting buffer register ch 0 R W 11111111B 0F9FH PDS00 8 16 bit PPG00 duty setting buffer register ch 0 R W 11111111B 0FA0H PPS11 8 16 bit PPG11 cycle setting buffer register ch 1 R W 111...

Page 39: ...DH to 0FDCH LCDRAM LCDC display RAM R W 00000000B 0FDDH to 0FE1H Disabled 0FE2H EVCR Event counter control register R W 00000000B 0FE3H WCDR Watch counter data register R W 00111111B 0FE4H CRTH Main C...

Page 40: ...circuit 8 16 bit composite timer ch 0 lower IRQ05 FFF0H FFF1H L05 1 0 8 16 bit composite timer ch 0 upper IRQ06 FFEEH FFEFH L06 1 0 IRQ07 FFECH FFEDH L07 1 0 IRQ08 FFEAH FFEBH L08 1 0 8 16 bit PPG ch...

Page 41: ...3 VSS 4 0 V 4 Maximum clamp current ICLAMP 2 0 2 0 mA Applicable to specific pins 5 Total maximum clamp current ICLAMP 20 mA Applicable to specific pins 5 L level maximum output cur rent IOL 15 mA Ap...

Page 42: ...he microcontroller drive current is low such as in low power consumption modes the HV High Voltage input potential may pass through the protective diode to increase the potential of the VCC pin and th...

Page 43: ...s use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made w...

Page 44: ...A0 to PA3 PB0 to PB7 PC0 to PC3 PC4 to PC7 1 PE0 to PE7 PG0 1 3 0 8 VCC VCC 0 3 V Hysteresis input VIHS2 P23 P24 3 0 8 VCC VSS 5 5 V VIHM RST 0 8 VCC VCC 0 3 V L level input voltage VIL P10 P23 P24 P9...

Page 45: ...5 V 5 A Pull up resis tance RPULL P00 to P03 P10 P11 P13 to P16 P20 to P22 P50 to P53 1 P94 P95 1 PG0 1 VI 0 0 V 25 50 100 k When pull up resistance is enabled Input capaci tance CIN Other than VCC a...

Page 46: ...atch mode Main stop mode TA 25 C 6 7 9 A ICCMPLL FCH 4 MHz FMP 10 MHz Main PLL mode multiplied by 2 5 10 1 19 2 mA FCH 6 4 MHz FMP 16 MHz Main PLL mode multiplied by 2 5 16 2 30 7 mA ICCMCR FCRH 12 5...

Page 47: ...ltage detection circuit the current consumption of the CR oscillators ICRH ICRL and a specified value In on chip debug mode the CR oscillator ICRH and the low voltage detection circuit are always enab...

Page 48: ...1875 12 5 12 8125 MHz Operating conditions The main CR clock is used TA 40 C to 10 C 9 75 10 10 25 MHz 7 8 8 8 2 MHz 0 975 1 1 025 MHz FCL X0A X1A 32 768 kHz When the sub oscillation circuit is used...

Page 49: ...hen the external clock is used X0 X1 X0 X1 FCH FCH When the external clock is used X1 is open X0 X1 Open FCH Figure of main clock input port external connection X0A 0 8 VCC 0 2 VCC 0 2 VCC 0 8 VCC tWH...

Page 50: ...Min FCRH 12 5 MHz Max FCRH 1 MHz 61 s When the sub oscillation clock is used FCL 32 768 kHz divided by 2 20 s When the sub CR clock is used FCRL 100 kHz divided by 2 Source clock fre quency FSP 0 50...

Page 51: ...lock divided by 4 Source clock divided by 8 Source clock divided by 16 FCH main oscillation FCRH Main CR clock FCL sub oscillation FCRL Sub CR clock SCLK source clock MCLK machine clock Clock mode sel...

Page 52: ...6 25 MHz Source clock frequency FSP FSPL Operating voltage V 3 6 2 7 1 8 16 kHz 3 MHz 5 MHz 16 25 MHz Source clock frequency FSP FSPL Operating voltage Operating frequency When TA 40 C to 85 C Without...

Page 53: ...llation time of an oscillator is the time for it to reach 90 of its amplitude The crystal oscillator has an oscillation time of between several ms and tens of ms The ceramic oscillator has an oscillat...

Page 54: ...ithin 20 mV ms as shown below Parameter Symbol Condition Value Unit Remarks Min Max Power supply rising time tR 50 ms Power supply cutoff time tOFF 1 ms Wait time until power on 0 2 VCC RST 0 2 VCC tR...

Page 55: ...al clock cycle time tSCYC UCK0 UCK1 Internal clock operation output pin CL 80 pF 1 TTL 4 tMCLK ns UCK UO time tSLOVI UCK0 UCK1 UO0 UO1 190 190 ns Valid UI UCK tIVSHI UCK0 UCK1 UI0 UI1 2 tMCLK ns UCK v...

Page 56: ...tSLOVI tIVSHI tSHIXI 2 4 V 0 8 V UCK0 UCK1 UO0 UO1 UI0 UI1 0 8 VCC 0 2 VCC 0 8 VCC 0 2 VCC tSCYC Internal shift clock mode 0 2 VCC 0 2 VCC 0 8 VCC 0 8 VCC tSLOVE tIVSHE tSHIXE 2 4 V 0 8 V UCK0 UCK1 U...

Page 57: ...rrupt release voltage 1 VIDL1 2 25 2 40 2 55 V At power supply rise Interrupt detection voltage 1 VIDL1 2 20 2 35 2 50 V At power supply fall Interrupt release voltage 2 VIDL2 2 46 2 61 2 76 V At powe...

Page 58: ...Parameter Symbol Value Unit Remarks Min Typ Max Power reset release delay time tdp1 10 300 s Power reset detection delay time tdp2 150 s Interrupt reset release delay time tdi1 10 200 s Interrupt rese...

Page 59: ...t the condition of tSU DAT 250 ns is fulfilled Continued Parameter Symbol Pin name Conditions Value Unit Standard mode Fast mode Min Max Min Max SCL clock frequency fSCL SCL0 R 1 7 k C 50 pF 1 0 100 0...

Page 60: ...ime in the device connected to the bus cannot be satisfied depending on the load capacitance or pull up resistor Be sure to adjust the pull up resistor of SDA0 and SCL0 if the rating of the input data...

Page 61: ...value is ap plied when m n 1 8 Otherwise the mini mum value is applied Stop condition setup time tSU STO SCL0 SDA0 1 nm 2 tMCLK 20 1 nm 2 tMCLK 20 ns Master mode Start condition setup time tSU STA SC...

Page 62: ...n detection tHD STA SCL0 SDA0 2 tMCLK 20 ns Not detected when 1 tMCLK is used at recep tion Stop condition detection tSU STO SCL0 SDA0 2 tMCLK 20 ns Not detected when 1 tMCLK is used at recep tion Res...

Page 63: ...5 MHz Fast mode m and n can be set to values in the following range 3 3 MHz tMCLK machine clock 16 25 MHz The usable frequencies of the machine clock are determined by the settings of m and n as shown...

Page 64: ...about 0 1 F to the analog input pin A D conversion error As VCC VSS decreases the A D conversion error increases proportionately 18 5 3 Definitions of A D Converter Terms Resolution It indicates the...

Page 65: ...l value The error can be caused by a zero transition error a full scale transition errors a linearity error a quantum error or noise Continued VFST Ideal I O characteristics 001H 002H 003H 004H 3FDH 3...

Page 66: ...nversion characteristic Actual conversion characteristic VFST measurement value VSS VCC VSS VCC VSS VCC VSS VCC Analog input Digital output Analog input Ideal characteristic 1 LSB N VOT Actual convers...

Page 67: ...test using the Arrhenius equation with the average temperature being 85 C Parameter Value Unit Remarks Min Typ Max Sector erase time 2 Kbyte sector 0 2 1 0 5 2 s The time of programming 00H prior to e...

Page 68: ...Hz 0 10 20 30 40 1 2 3 4 5 I CCL A VCC V ICC VCC TA 25 C FMP 2 4 8 10 16 MHz divided by 2 Main clock mode with the external clock operating ICC TA VCC 3 0 V FMP 10 16 MHz divided by 2 Main clock mode...

Page 69: ...CC V 0 25 50 75 100 1 2 3 4 5 I CCT A VCC V 0 2 4 6 10 8 1 2 3 4 5 I CTS mA VCC V FMP 16 MHz FMP 10 MHz FMP 8 MHz FMP 4 MHz FMP 2 MHz 0 2 4 6 10 8 50 0 50 100 150 I CTS mA TA C FMP 16 MHz FMP 10 MHz I...

Page 70: ...140 1 2 3 4 5 I CCSCR A VCC V 0 20 80 60 40 100 120 160 140 50 0 50 100 150 I CCSCR A TA C ICCMCR VCC TA 25 C FMP 1 8 10 12 5 MHz no division Main clock mode with the main CR clock operating ICCMCR TA...

Page 71: ...2 4 3 1 2 3 4 5 V IHI2 V IL V VCC V VIHI2 VIL VIHI1 VCC and VIL VCC TA 25 C VIHI2 VCC and VIL VCC TA 25 C 0 1 2 4 3 1 2 3 4 5 V IHS1 V ILS V VCC V VIHS1 VILS VIHS1 VCC and VILS VCC TA 25 C 0 1 2 4 3 1...

Page 72: ...e characteristics 0 2 4 IOL mA 6 8 10 1 0 0 8 0 6 V OL V 0 4 0 2 0 0 VCC 1 8 V VCC 2 0 V VCC 2 4 V VCC 2 7 V VCC 3 0 V VCC 3 6 V VOL IOL TA 25 C 0 2 4 IOH mA 6 8 10 1 0 0 8 0 6 V CC V OH V 0 4 0 2 0 0...

Page 73: ...Low voltage detection reset With low voltage detection reset Without low voltage detection reset Part Number Package MB95F314EPMC G SNE2 MB95F314LPMC G SNE2 MB95F316EPMC G SNE2 MB95F316LPMC G SNE2 MB9...

Page 74: ...ocument Number 002 07519 Rev A Page 74 of 80 MB95F374EPMC2 G SNE2 MB95F374LPMC2 G SNE2 MB95F376EPMC2 G SNE2 MB95F376LPMC2 G SNE2 MB95F378EPMC2 G SNE2 MB95F378LPMC2 G SNE2 64 pin plastic LQFP FPT 64P M...

Page 75: ...DUCTOR LIMITED F80037S c 1 2 1 20 40 21 60 41 80 61 INDEX 12 00 0 10 472 004 SQ 14 00 0 20 551 008 SQ 0 50 020 0 22 0 05 009 002 M 0 08 003 0 145 0 055 006 002 0 08 003 A Stand off Details of A part 0...

Page 76: ...55 0 08 003 M 009 002 0 22 0 05 0 50 020 12 00 0 20 472 008 SQ 10 00 0 10 394 004 SQ INDEX 49 64 33 48 17 32 16 1 2010 FUJITSU SEMICONDUCTOR LIMITED F64038S c 1 2 Stand off Details of A part 004 004 0...

Page 77: ...64P M39 FPT 64P M39 A 0 10 004 006 002 0 145 0 055 0 13 005 M 013 002 0 32 0 05 0 65 026 14 00 0 20 551 008 SQ 12 00 0 10 472 004 SQ INDEX 49 64 33 48 17 32 16 1 2010 2011 FUJITSU SEMICONDUCTOR LIMIT...

Page 78: ...er supply current ICCSCR FCL 32 kHz FMPL 16 kHz Sub CR clock mode divided by 2 TA 25 C Sub CR clock mode divided by 2 TA 25 C 47 Changed the condition for the power supply current ICRH Current consump...

Page 79: ...4E F374L F376E F376L F378E F378L New 8FX MB95310L 370L Series 8 bit Microcontrollers Document Number 002 07519 Revision ECN Orig of Change Submission Date Description of Change AKIH 08 13 2010 Migrate...

Page 80: ...ent including any sample design information or programming code is provided only for reference purposes It is the responsibility of the user of this document to properly design program and test the fu...

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