MB95310L/370L Series
Document Number: 002-07519 Rev. *A
Page 33 of 80
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0FA4
H
PPGS
8/16-bit PPG start register
R/W
00000000
B
0FA5
H
REVC
8/16-bit PPG output inversion register
R/W
00000000
B
0FA6
H
TMRH0
16-bit reload timer timer register upper
R/W
00000000
B
TMRLRH0
16-bit reload timer reload register upper
R/W
00000000
B
0FA7
H
TMRL0
16-bit reload timer timer register lower
R/W
00000000
B
TMRLRL0
16-bit reload timer reload register lower
R/W
00000000
B
0FA8
H
to
0FBD
H
—
(Disabled)
—
—
0FBE
H
PSSR0
UART/SIO dedicated baud rate generator prescaler selecting register ch. 0
R/W
00000000
B
0FBF
H
BRSR0
UART/SIO dedicated baud rate generator baud rate setting register ch. 0
R/W
00000000
B
0FC0
H
PSSR1
UART/SIO dedicated baud rate generator prescaler selecting register ch. 1
R/W
00000000
B
0FC1
H
BRSR1
UART/SIO dedicated baud rate generator baud rate setting register ch. 1
R/W
00000000
B
0FC2
H
—
(Disabled)
—
—
0FC3
H
AIDRL
A/D input disable register (lower)
R/W
00000000
B
0FC4
H
LCDCC
LCDC control register
R/W
00010000
B
0FC5
H
LCDCE1
LCDC enable register 1
R/W
00110000
B
0FC6
H
LCDCE2
LCDC enable register 2
R/W
00000000
B
0FC7
H
LCDCE3
LCDC enable register 3
R/W
00000000
B
0FC8
H
LCDCE4
LCDC enable register 4
R/W
00000000
B
0FC9
H
LCDCE5
LCDC enable register 5
R/W
00000000
B
0FCA
H
LCDCE6
LCDC enable register 6
R/W
00000000
B
0FCB
H
LCDCB1
LCDC blinking setting register 1
R/W
00000000
B
0FCC
H
LCDCB2
LCDC blinking setting register 2
R/W
00000000
B
0FCD
H
to
0FE0
H
LCDRAM
LCDC display RAM
R/W
00000000
B
0FE1
H
—
(Disabled)
—
—
0FE2
H
EVCR
Event counter control register
R/W
00000000
B
0FE3
H
WCDR
Watch counter data register
R/W
00111111
B
0FE4
H
CRTH
Main CR clock trimming register (upper)
R/W
0XXXXXXX
B
0FE5
H
CRTL
Main CR clock trimming register (lower)
R/W
00XXXXXX
B
0FE6
H
to
0FE8
H
—
(Disabled)
—
—
0FE9
H
CMCR
Clock monitoring control register
R/W
XX000000
B
0FEA
H
CMDR
Clock monitoring data register
R
00000000
B