MB95310L/370L Series
Document Number: 002-07519 Rev. *A
Page 64 of 80
18.5.2
Notes on Using the A/D Converter
■
External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the
analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion
precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external imped-
ance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance
so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
■
A/D conversion error
As |V
CC
V
SS
| decreases, the A/D conversion error increases proportionately.
18.5.3
Definitions of A/D Converter Terms
■
Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 2
10
= 1024.
■
Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
Note: The values are reference values.
2.7 V
≤
V
CC
≤
3.6V
1.8 V
≤
V
CC
<
2.7 V
1.7 k
Ω
(Max)
8.4 k
Ω
(Max)
14.5 pF (Max)
V
CC
R
C
25.2 pF (Max)
Comparator
Analog input
During sampling: ON
R
C
• Analog input equivalent circuit
[External impedance = 0 k
Ω
to 100 k
Ω
]
Exter
nal impedance [k
Ω
]
Exter
nal impedance [k
Ω
]
Minimum sampling time [
μ
s]
Minimum sampling time [
μ
s]
[External impedance = 0 k
Ω
to 20 k
Ω
]
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
35
1
0
2
3
4
(V
CC
≥
2.7 V)
(V
CC
≥
1.8 V)
(V
CC
≥
2.7 V)
• Relationship between external impedance and minimum sampling time
