Cypress MB95310L Series, Manual

Page: 39 / 80

MB95310L/370L Series
Document Number: 002-07519 Rev. *A Page 39 of 80
(Continued)
■
R/W access symbols
■
Initial value symbols
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
Address
Register
abbreviation
Register name R/W Initial value
0FC5
H
LCDCE1 LCDC enable register 1 R/W 00110000
B
0FC6
H
LCDCE2 LCDC enable register 2 R/W 00000000
B
0FC7
H
LCDCE3 LCDC enable register 3 R/W 00000000
B
0FC8
H
LCDCE4 LCDC enable register 4 R/W 00000000
B
0FC9
H
LCDCE5 LCDC enable register 5 R/W 00000000
B
0FCA
H
— (Disabled) — —
0FCB
H
LCDCB1 LCDC blinking setting register 1 R/W 00000000
B
0FCC
H
LCDCB2 LCDC blinking setting register 2 R/W 00000000
B
0FCD
H
to
0FDC
H
LCDRAM LCDC display RAM R/W 00000000
B
0FDD
H
to
0FE1
H
— (Disabled) — —
0FE2
H
EVCR Event counter control register R/W 00000000
B
0FE3
H
WCDR Watch counter data register R/W 00111111
B
0FE4
H
CRTH Main CR clock trimming register (upper) R/W 0XXXXXXX
B
0FE5
H
CRTL Main CR clock trimming register (lower) R/W 00XXXXXX
B
0FE6
H
to
0FE8
H
— (Disabled) — —
0FE9
H
CMCR Clock monitoring control register R/W XX000000
B
0FEA
H
CMDR Clock monitoring data register R 00000000
B
0FEB
H
WDTH Watchdog timer selection ID register (upper) R XXXXXXXX
B
0FEC
H
WDTL Watchdog timer selection ID register (lower) R XXXXXXXX
B
0FED
H
— (Disabled) — —
0FEE
H
ILSR Input level select register R/W 00000000
B
0FEF
H
WICR Interrupt pin control register R/W 01000000
B
0FF0
H
to
0FFF
H
— (Disabled) — —
R/W : Readable / Writable
R : Read only
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is indeterminate.