Cypress MB95310L Series, Manual

Page: 63 / 80

MB95310L/370L Series
Document Number: 002-07519 Rev. *A Page 63 of 80
(Continued)
*1: R represents the pull-up resistor of the SCL0 and SDA0 lines, and C the load capacitor of the SCL0 and SDA0 lines.
*2: • See “(2) Source Clock/Machine Clock” for t
MCLK
.
• m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I
2
C clock control register (ICCR0).
• n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I
2
C clock control register (ICCR0).
• The actual timing of I
2
C is determined by the values of m and n set by the machine clock (t
MCLK
) and the CS4 to CS0 bits in the
ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < t
MCLK
(machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8): 0.9 MHz < t
MCLK

1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4): 0.9 MHz < t
MCLK

2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8): 0.9 MHz < t
MCLK

4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22): 0.9 MHz < t
MCLK

10 MHz
(m, n) = (8, 22): 0.9 MHz < t
MCLK

16.25 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < t
MCLK
(machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8): 3.3 MHz < t
MCLK

4 MHz
(m, n) = (1, 22), (5, 4): 3.3 MHz < t
MCLK

8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4): 3.3 MHz < t
MCLK

10 MHz
(m, n) = (5, 8): 3.3 MHz < t
MCLK

16.25 MHz
18.5 A/D Converter
18.5.1 A/D Converter Electrical Characteristics
(V
CC
= 1.8 V to 3.6 V, V
SS
= 0.0 V, T
A
=

40

C to

85

C)
Parameter Symbol
Value
Unit Remarks
Min Typ Max
Resolution
—
— — 10 bit
Total error

3 —

3 LSB
Linearity error

2.5 —

2.5 LSB
Differential linear
error

1.9 —

1.9 LSB
Zero transition
voltage
V
OT
AV
SS

1.5 LSB AV
SS

0.5 LSB AV
SS

2.5 LSB V 2.7 V

V
CC

3.6 V
AV
SS

0.5 LSB AV
SS

1.5 LSB AV
SS

3.5 LSB V 1.8 V

V
CC
<

2.7 V
Full-scale transition volt-
age
V
FST
AV
CC

3.5 LSB AV
CC

1.5 LSB AV
CC

0.5 LSB V 2.7 V

V
CC

3.6 V
AV
CC

2.5 LSB AV
CC

0.5 LSB AV
CC

1.5 LSB V 1.8 V

V
CC
<

2.7 V
Compare time —
0.6 — 140 µs 2.7 V

V
CC

3.6 V
20 — 140 µs 1.8 V

V
CC
<

2.7 V
Sampling time —
0.4 —

µs
2.7 V

V
CC

3.6 V, with external im-
pedance < 1.8 k

30 —

µs
1.8 V

V
CC
<

2.7 V, with external im-
pedance < 14.8 k

Analog input current I
AIN

0.3 —

0.3 µA
Analog input voltage V
AIN
AV
SS
— AV
CC
V