Technical Description
DIGITAL PowerStorm 1000 Graphics Subsystem Owner's Guide 6–7
Each pixel link contains RGB, alpha, stencil, and Z values plus a pointer to the next
link. Links are stored in receding Z order. These lists are the heart of the HiFIVE anti-
aliasing system, eliminating the need for presorting primitives and multi-pass
algorithms by retaining enough information at multiple Z depths. Figure 6-2 illustrates
an Image Rendering Module block diagram.
While the fragment modification calculations for texture mapping are part of the SSLD
ASIC, the actual mipmap storage is in separate memory on the Texture Memory Modules.
All Image Rendering Modules in a PowerStorm 1000 graphics subsystem must have the
same amount of texture memory, either 32 MB or 64 MB.
Figure 6-2 Image Rendering Module Block Diagram
46
Super Slicer
(SSD)
64
3D Blender
(SAM)
PLM
PLM
3D Blender
(SAM)
PLM
64
PLM
32
32
TM
TM
Input from
VDM ASIC
Optional
112
fragment broadcast
xyrgb or control
RC
ML014290