BGS3 Hardware Interface Description
3.11 Audio Interfaces
63
BGS3_HD_v01.000d
Page 59 of 109
2010-03-26
Confidential / Released
The timing of a PCM
long frame
is shown in
. The 16-bit TXDAI and RXDAI data is
transferred simultaneously in both directions while the frame sync pulse FS is high. For this rea-
son the duration of a frame sync pulse is 16 BITCLK periods, starting at the rising edge of BIT-
CLK. TXDAI data is shifted out at the same rising edge of BITCLK. RXDAI data (i.e. data
transmitted from the host application to the module's RXDAI line) is sampled at the falling edge
of BITCLK.
Figure 22:
Long Frame PCM timing
3.11.4.2
Slave Mode
In slave mode the PCM interface is controlled by an external bit clock and an external frame
sync signal applied to the BCLKIN and FSIN lines and delivered either by the connected codec
or another source. The bit clock frequency has to be in the range of 256kHz -125ppm to 512kHz
+125ppm.
Data transfer starts at the falling edge of FSIN if the short frame format is selected, and at the
rising edge of FSIN if long frame format is selected. With this edge control the frame sync signal
is independent of the frame sync pulse length.
TXDAI data is shifted out at the rising edge of BCLKIN. RXDAI data (i.e. data transmitted from
the host application to the module's RXDAI line) is sampled at the falling edge of BCLKIN.
The deviation of the external frame rate from the internal frame rate must not exceed ±125ppm.
The internal frame rate of nominal 8kHz is synchronized to the GSM network.
The difference between the internal and the external frame rate is equalized by doubling or
skipping samples. This happens for example every second, if the difference is 125ppm.
The resulting distortion can be neglected in speech signals.
The lines BITCLK and FS remain low in slave mode.
The below
shows the typical slave configuration. The external codec delivers the bit
clock and the frame sync signal. If the codec itself is not able to run in master mode as for ex-
ample the MC145483, a third party has to generate the clock and the frame sync signal.
