BGS3 Hardware Interface Description
3.11 Audio Interfaces
63
BGS3_HD_v01.000d
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2010-03-26
Confidential / Released
3.11.4.1
Master Mode
To clock input and output PCM samples the PCM interface delivers a bit clock (BITCLK) which
is synchronous to the GSM system clock. The frequency of the bit clock is 256kHz or 512kHz.
Any edge of this clock deviates less than ±100ns (Jitter) from an ideal 256-kHz clock respec-
tively deviates less than ±320ns from an ideal 512-kHz clock.
The frame sync signal (FS) has a frequency of 8kHz and is high for one BITCLK period before
the data transmission starts if short frame is configured. If long frame is selected the frame sync
signal (FS) is high during the whole transfer of the 16 data bits. Each frame has a duration of
125µs and contains 32 respective 64 clock cycles.
Figure 20:
Master PCM interface Application
The timing of a PCM
short frame
is shown in
. The 16-bit TXDAI and RXDAI data is
transferred simultaneously in both directions during the first 16 clock cycles after the frame
sync pulse. The duration of a frame sync pulse is one BITCLK period, starting at the rising edge
of BITCLK. TXDAI data is shifted out at the next rising edge of BITCLK. RXDAI data (i.e. data
transmitted from the host application to the module's RXDAI line) is sampled at the falling edge
of BITCLK.
Figure 21:
Short Frame PCM timing
