Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1724 8 Channel 14bit - 100MS/s Digitizer
06/11/2007
7
NPO:
Filename:
Number of pages:
Page:
00103/05:V1724x.MUTx/07 V1724_REV7.DOC
63
8
1. General description
1.1. Overview
The Mod. V1724 is a 1-unit wide VME 6U module housing a 8 Channel 14 bit 100 MS/s
Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities.
The board is available with different input range, memory and connector configuration, as
summarised by the following table:
Table 1.1: Mod. V1724 versions
Model
Input type
SRAM Memory
Optical link
AMC FPGA(*)
Form factor
V1724LC
Single ended 512 Ksamples / ch
No
EP1C4
6U-VME64
V1724
Single ended 512 Ksamples / ch
Yes
EP1C4
6U-VME64
V1724B
Single ended 4 Msamples / ch
Yes
EP1C4
6U-VME64
V1724C
Differential
512 Ksamples / ch
Yes
EP1C4
6U-VME64
V1724D
Differential
4 Msamples / ch
Yes
EP1C4
6U-VME64
V1724E
Single ended 4 Msamples / ch
Yes
EP1C20
6U-VME64
V1724F
Differential
4 Msamples / ch
Yes
EP1C20
6U-VME64
VX1724
Single ended 512 Ksamples / ch
Yes
EP1C4
6U-VME64X
VX1724B
Single ended 4 Msamples / ch
Yes
EP1C4
6U-VME64X
VX1724C
Differential
512 Ksamples / ch
Yes
EP1C4
6U-VME64X
VX1724D
Differential
4 Msamples / ch
Yes
EP1C4
6U-VME64X
VX1724E
Single ended 4 Msamples / ch
Yes
EP1C20
6U-VME64X
VX1724F
Differential
4 Msamples / ch
Yes
EP1C20
6U-VME64X
(*)
AMC: ADC e Memory controller FPGA. Models available: ALTERA Cyclone EP1C4 (4000 Logic elements)
or ALTERA Cyclone EP1C20 (20000 Logic elements).
Single ended input versions, optionally, are available with 10 Vpp dynamic range (default
range: 2.25 Vpp).
The DC offset of the signal can be adjusted channel per channel by means of a
programmable 16bit DAC.
The board features a front panel clock/reference In/Out and a PLL for clock synthesis
from internal/external references. This allows multi board phase synchronisations to an
external clock source or to a V1724 clock master board.
The data stream is continuously written in a circular memory buffer; when the trigger
occurs the FPGA writes further N samples for the post trigger and freezes the buffer that
then can be read either via VME or via Optical Link; the acquisition can continue without
dead-time in a new buffer. Each channel has a SRAM memory, divided in buffers of
programmable size.
The trigger signal can be provided via the front panel input as well as via the VMEbus,
but it can also be generated internally, as soon as a programmable voltage threshold is
reached. The individual Auto-Trigger of one channel can be propagated to the other
channels and onto the front panel Trigger Output.
The VME interface is VME64X compliant and the data readout can be performed in