Caen V1724 Series, Technical Information Manual, Page: 22 / 63

P R E L I M I N A R Y
Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 7
NPO: Filename: Number of pages: Page:
00103/05:V1724x.MUTx/07 V1724_REV7.DOC 63 22
3.3.3. Sample mode
In Sample mode only the first value sampled after the S-IN signal leading edge is stored;
; data storage takes place by couples of samples (two 32 bit long words) per time. For
this purpose it is necessary to:
−
Set bits [1:0] of Acquisition Control register to S-IN GATE MODE
−
Set bit [0] of Channel Configuration Register (see § 4.12) to 1
Note that, if the S-IN signal is not synchronised with the sampling clock, then a 1 clock
period jitter occurs between the S-IN leading edge and the actual sampling time.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
SAMPLING CLOCK
S-IN
ADC DATA
S0
S4
S8
S12
S16
S20
S24
S28
S 32
S36
S40
D11 D12
S44
S48
S52
D1 D1 D1 D1 D1
D5 D1
D5 D1
D5 D1
D5 D1
D5
D9 D1
D5
D9 D1
D5
D9
MEMORY
BUFFER
D1
D5
D9
Fig. 3.6: Data storage
2
in Sample Mode
3.3.4. Acquisition Triggering: Samples and Events
When the acquisition is running, a trigger signal allows to:
−
store a Trigger Time Tag (TTT): the value of a 32 bit counter which steps on with
the sampling clock and represents a time reference
−
increment the EVENT COUNTER (see § 4.29)
−
fill the active buffer with the pre/post-trigger samples, whose number is
programmable via Post Trigger Setting register (see § 4.23); the Acquisition window
width is determined via Buffer Organization register setting (see § 4.15,); then the
buffer is frozen for readout purposes, while acquisition continues on another buffer.
Table 3.1: Buffer Organization
SIZE of one BUFFER (samples) REGISTER
(see § 4.15)
BUFFER NUMBER
SRAM 1MB/ch (512KS) SRAM 8MB/ch (4MS)
0x00 1 512K 4M
0x01 2 256K 2M
0x02 4 128K 1M
0x03 8 64K 512K
0x04 16 32K 256K
0x05 32 16K 128K
0x06 64 8K 64K
0x07 128 4K 32K
0x08 256 2K 16K
0x09 512 1K 8K
0x0A 1024 512 4K
2
Underscored = stored