A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
PCI9052RDK-LITE BLOCK DIAGRAM
ECN HISTORY
ECN NUMBER
DATE
NOTE
PCI9052
PG 3
LOCAL BUS
PCI BUS ( PCI Edge connector, PG 2)
000
1/11/2000
Started the project
Up to 40MHz
33MHz
Socketed 1K
Serial
EEPROM
Prototype
Footprints
PG6-9
Test Headers
PG5
Prototyping
ROM Socket
PG4
User
Programable
Logic
PG4
ISA Interface
Connector
PG4
128KB SRAM
(32K x 32)
PG4
001
18/04/2001
First Production
002
7/08/2002
Update RN20, RN21, RN22 from 10K to 1K on sheet 4 to reflect the BOM
Update the BOM and schematic document number
Update U6 from 93CS46L to 93LC46B to reflect the BOM
Changed LRESET# to LRESET for ISA interface Mode
002
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
Custom
1
9
Friday, July 12, 2002
www.plxtech.com
91-0023-002-A
Electrical Block Diagram
Title
Size
Document Number
Rev
Date:
Sheet
of
Summary of Contents for PLX PCI 9052RDK-LITE
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