Broadcom PLX PCI 9052RDK-LITE, Hardware Reference Manual

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Table 3-4. Configuration Jumper Settings
Function Option Jumper
Location
Jumper
Setting
Jumper
Default
Local Bus Operation ISA
1
Non-Multiplexed
Multiplexed
JP5 2-3
2-3
1-2
X
Local Interrupt 1 (LINTi1) Termination LINTi1 Active High
LINTi1 Active Low
JP3 2-3
1-2
X
Local Interrupt 2 (LINTi2) Termination LINTi2 Active High
LINTi2 Active Low
JP4 2-3
1-2
X
Local Interrupt 1 (LINTi1) Routing ISA_INT to LINTi1
XINT1 to LINTi1
CHCHK# to LINTi1
XINT2 to LINTi1
JP1 9-10
11-12
13-12
15-12
X
Local Interrupt 2 (LINTi2) Routing ISA_INT to LINTi2
XINT1 to LINTi2
CHCHK# to LINTi2
XINT2 to LINTi2
JP1 9-14
11-14
13-14
15-16
Local Clock Source BCLKo
8 MHz
16 MHz
32 MHz
JP1 7-8
1-2
3-4
5-6
X
Chip Select Routing CS0# to CSRAM#
CS0# to CSROM#
CS1# to CSRAM#
CS1# to CSROM#
CS2# to CSRAM#
CS2# to CSROM#
CS3# to CSRAM#
CS3# to CSROM#
JP2 1-10
1-14
5-10
5-14
9-10
9-14
13-10
13-14
X
X
ROM Socket VCC Vcc = 5 V
Vcc = 3.3 V
JP6 1-2
2-3
NOWS# Delay Disabled
Enabled
JP7 1-2
2-3
X
Note 1 . ISA Mode is selected by setting Jumper JP5 2-3 and programming INTCSR[12]=1 in the EEPROM. The
board ships with INTCSR[12]=1.
Note 2 . If the jumper between pins 9 and 10 of JP2 is removed, the CSRAM# input to the CPLD will be floating
without an external pull-up resistor. That may cause the CPLD to generate incorrect RCS[3:0]# chip select signals to
the local bus SRAM. Similarly, if the jumper between pins 13 and 14 of JP2 is removed, the CSROM# input to the
CPLD will be floating without an external pull-up resistor. That may cause the CPLD to generate an incorrect
CSROMO# chip select signal to the Local bus ROM socket.
Note 3. When operating the 9052 with local clock below 16MHz (for example 8MHz) ensure that either CNTRL[14]=1
and/or CNTRL[22:19]=Fh in the EEPROM. Failure to do so may result in the card failing to boot in some systems.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved . 13