Broadcom PLX PCI 9052RDK-LITE, Hardware Reference Manual

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Serial
EEPROM
Register Bits Register
Register
Register Description Register Value Description
Offset
Offset
Affected Values
38h Local 2Ah
MSW of Bus Region Descriptors for
Local Address Space 0
LAS0BRD [31:16] 0040
3Ah Local 28h
LSW of Bus Region Descriptors for
Local Address Space 0
LAS0BRD [15:0] 0022
Sets bus width to 16 for ISA Memory
space accesses. No prefetching.
3Ch Local 2Eh
MSW of Bus Region Descriptors for
Local Address Space 1
LAS1BRD [31:16] 0000
3Eh Local 2Ch
LSW of Bus Region Descriptors for
Local Address Space 1
LAS1BRD [15:0] 0022
Sets bus width to 8 for ISA I/O space
accesses. No prefetching.
40h Local 32h
MSW of Bus Region Descriptors for
Local Address Space 2
LAS2BRD [31:16] 0080
Enables bursting & sets bus width to 32
for RDK SRAM. Prefetch enabled.
42h Local 30h
LSW of Bus Region Descriptors for
Local Address Space 2
LAS2BRD [15:0] 0001
44h Local 36h
MSW of Bus Region Descriptors for
Local Address Space 3
LAS3BRD [31:16] 5421
46h Local 34h
LSW of Bus Region Descriptors for
Local Address Space 3
LAS3BRD [15:0] 38E9
Sets timing & bus width to 8 for RDK
ROM. Burst enabled, Prefetch enabled,
Prefetch count=1, NRAD=3, NRDD=3,
NXDA=1, NWAD=2, NWDD=2, RSD=1,
WSD=1, WCH=1
48h Local 3Ah
MSW of Bus Region Descriptors for
Expansion ROM
EROMBRD [31:16] 0
4Ah Local 38h
LSW of Bus Region Descriptors for
Expansion ROM
EROMBRD [15:0] 0
No Expansion ROM enabled
4Ch Local 3Eh
MSW of Chip Select (CS) 0
Base and Range
CS0BASE [31:16] 0008
4Eh Local 3Ch
LSW of Chip Select (CS) 0
Base and Range
CS0BASE [15:0] 0001
As a default this CS is not active as its
pin is used as an ISA bus signal. The
local address range is set from
00000000 to 000FFFFFh to allow
correct ISA Memory space accesses.
50h Local 42h
MSW of Chip Select (CS) 1
Base and Range
CS1BASE [31:16] 0000
52h Local 40h
LSW of Chip Select (CS) 1
Base and Range
CS1BASE [15:0] 0009
As a default this CS is not active as its
pin is used as an ISA bus signal. The
local address range is set from
00000000 to 0000000Fh to allow
correct ISA I/O space accesses.
54h Local 46h
MSW of Chip Select (CS) 2
Base and Range
CS2BASE [31:16] 0101
56h Local 44h
LSW of Chip Select (CS) 2
Base and Range
CS2BASE [15:0] 0001
This CS is active from local address
01000000 to 0101FFFFh
for RDK SRAM
58h Local 4Ah
MSW of Chip Select (CS) 3
Base and Range
CS3BASE [31:16] 0208
5Ah Local 48h
LSW of Chip Select (CS) 3
Base and Range
CS3BASE [15:0] 0001
This CS is active from local address
02000000 to 020FFFFFh
for RDK ROM
5Ch Local 4Eh
MSW of Interrupt Control/Status
Register
INTCSR [31:16] 0000
5Eh Local 4Ch
LSW of Interrupt Control/Status
Register
INTCSR [15:0] 115B
Local interrupt 1 enabled, active high
level sensitive. Local interrupt 2
enabled, active high level sensitive.
ISA mode.
60h Local 52h
MSW of Serial EEPROM, control and
miscellaneous control register
CNTRL [31:16] 007C
62h Local 50h
LSW of Serial EEPROM, control and
miscellaneous control register
CNTRL [15:0] 4252
CS and User pin configuration, ISA I/O
pin configuration, CS2 & CS3 active,
RDK occupies PCI memory & I/O
space, PCI 2.1 features enabled,
PCI Write release enabled,
PCI Direct Slave Retry Delay = Fh.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
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© 2004 PLX Technology, Inc. All rights reserved.