Broadcom PLX PCI 9052RDK-LITE, Hardware Reference Manual

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3.2 Hardware Memory Map
Table 3-1. PCI 9052RDK-LITE Default Memory Map
Address Range Device Chip Select Comments
0FFF FFFF
0300 0000
Unused Unused Unused
020F FFFF
0200 0000
ROM Socket CS3#
0101 FFFF
0100 0000
SRAM CS2#
000F FFFF
0000 0000
ISA Memory space
0000 000F
0000 0000
ISA I/O space
CS0# & CS1#
In ISA mode the
CS0# & CS1#
pins are
redefined as
MEMRD# and
MEMWR#,
respectively
The address range over which each CSn# is active can be changed by reprogramming the on-board
serial EEPROM. Refer to Table 3-2 Serial EEPROM Contents for a description of the PCI 9052 address
space registers. The SRAM and ROM chip selects can be driven by any PCI 9052 chip select signal.
Refer to Table 3-4 Configuration Jumper Settings to choose a different chip select signal for ROM and
SRAM accesses.
3.3 Serial EEPROM
A 1Kbit serial EEPROM is used for RDK board configuration and PCI 9052 initialization. The serial
EEPROM is connected to the PCI 9052 without any glue logic. The preprogrammed data in the EEPROM
is used to configure the RDK board during boot up. The data includes device and functional information
for plug-and-play (PnP), PCI memory resource allocation and initial values of PCI 9052 internal registers.
Once the RDK initialization is completed, designers can use PLXMon
®
to change the contents in the
serial EEPROM or reprogram it with user defined data files.
If the Local Clock (LCLK) frequency is set to 8 MHz (JP1[1:2]), rather than to 16-, 32-, or 33-MHz, a
programmed serial EEPROM is required in order to boot the system. If the serial EEPROM is either
missing or blank, PCI 9052 default register values are loaded, and these values enable Expansion ROM
memory and disable delayed reads. At boot time, the BIOS will access the Expansion ROM space;
however, with LCLK at 8 MHz, the PCI 9052RDK-Lite cannot complete the Expansion ROM access prior
to expiration of the Retry Delay Clocks counter. With the programmed EEPROM, the Expansion ROM
request is disabled and delayed reads are enabled to allow booting at reduced LCLK frequency.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
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© 2004 PLX Technology, Inc. All rights reserved.