Broadcom PLX PCI 9052RDK-LITE Hardware Reference Manual Download Page 3 | Manualshive

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PCI 9052RDK-LITE

Hardware Reference Manual

Version 1.3

October 2004

Website:

http://www.plxtech.com

Technical Support:

http://www.plxtech.com/support/

Phone:

408 774-9060

800 759-3735

Fax:

408 774-2169

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Summary of Contents for PLX PCI 9052RDK-LITE

Page 1: ...PCI 9052RDK LITE Hardware Reference Manual...

Page 2: ......

Page 3: ...PCI 9052RDK LITE Hardware Reference Manual Version 1 3 October 2004 Website http www plxtech com Technical Support http www plxtech com support Phone 408 774 9060 800 759 3735 Fax 408 774 2169...

Page 4: ...to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX products PLX Technology and the PLX logo are registere...

Page 5: ...ocument describes the PLX PCI 9052RDK LITE a Rapid Development Kit from a hardware perspective It contains a description of all major functional circuit blocks on the board and also is a reference for...

Page 6: ......

Page 7: ...ON 15 4 1 1 Range Register 15 4 1 2 Base Address Re map Register 15 4 1 3 Chip Select Register 15 4 2 ISA REGISTER CONFIGURATION EXAMPLE 16 4 2 1 ISA Memory Mapping 16 4 2 2 ISA I O Mapping 16 4 2 3 C...

Page 8: ...ersion 12 LIST OF TABLES Table 3 1 PCI 9052RDK LITE Default Memory Map 6 Table 3 2 Serial EEPROM Contents 7 Table 3 3 PCI 9052RDK LITE Board Prototyping Area Footprints 11 Table 3 4 Configuration Jump...

Page 9: ...These allow designers to test simulate and debug their designs without fabricating their own boards saving considerable time and money in the development process and shortening time to market The RDK...

Page 10: ...l bus clock 5V to 3 3V voltage regulator Six logic analyzer headers with standard HP footprint to allow easy probing of local bus signals 25x25 0 1 through hole prototyping grid 1 2 RDK Installation T...

Page 11: ...I clock allowing the local bus to be run at an independent rate The buffered PCI bus clock output BCLKO may be connected to the local bus clock LCLK input through a 50 Ohm series resistor if desired P...

Page 12: ...fetch counter The local bus pre fetch counter can be programmed for 0 no pre fetch 4 8 16 or Continuous Pre fetch Mode pre fetch counter turned off The pre fetched data can be used as cached data if...

Page 13: ...PCI 9052 burst read write accesses to 128 Kbytes of SRAM provided in a 32 bit wide format An inexpensive 64 macrocell CPLD is used to generate various control signals for the RDK board While not requi...

Page 14: ...he preprogrammed data in the EEPROM is used to configure the RDK board during boot up The data includes device and functional information for plug and play PnP PCI memory resource allocation and initi...

Page 15: ...e 3 LAS3RR 31 16 FFF0 1Eh Local 0Ch LSW of Range for PCI to Local Address Space 3 LAS3RR 15 0 0000 1MB local address space for the RDK memory mapped ROM mapped into PCI memory space 20h Local 12h MSW...

Page 16: ...CS0BASE 15 0 0001 As a default this CS is not active as its pin is used as an ISA bus signal The local address range is set from 00000000 to 000FFFFFh to allow correct ISA Memory space accesses 50h L...

Page 17: ...are a few minor exceptions to ISA compatibility The PCI 9052RDK LITE board does not provide 5V to the ISA interface connector Also the PCI 9052 does not support ISA mastering nor ISA DMA operations L...

Page 18: ...interface the PCI 9052 to the ISA bus using a small CPLD makes the RDK as flexible as possible as a development platform It performs the following functions Clock division to generate 16 MHz and 8 MHz...

Page 19: ...8 15 16 54 pin TSOP 2 0 8mm pitch FP9 10 48 pin SSOP 2 300 wide 0 025 pitch FP23 24 20 pin SOIC wide 4 300 wide 0 05 pitch FP17 18 19 20 24 pin SSOP 2 150 wide 0 025 pitch FP21 22 44 pin TQFP 1 0 8mm...

Page 20: ...nd the Land Socket plugged into the Minigrid Socket These sockets are available from Ironwood Electronics web site www ironwoodelectronics com BGA Device Ironwood BGA Land Socket Ironwood Minigrid Soc...

Page 21: ...3 10 13 14 X X ROM Socket VCC Vcc 5 V Vcc 3 3 V JP6 1 2 2 3 NOWS Delay Disabled Enabled JP7 1 2 2 3 X Note 1 ISA Mode is selected by setting Jumper JP5 2 3 and programming INTCSR 12 1 in the EEPROM Th...

Page 22: ......

Page 23: ...address programmed into the LASxBA register must be a multiple of the appropriate range or 0 This restriction may require lowering the base address and increasing the range to ensure that both the IS...

Page 24: ...s to be set to cover the memory mapped region in Local Address Space 0 Based on the method described in section 4 1 3 the CS0BASE register value should be 0x00001201h Similarly the CS1BASE register ha...

Page 25: ...s a correctly programmed EEPROM is present 4 2 7 PCI Access to Local ISA Bus PCIBAR 0 and 1 are the addresses of the PCI 9052 registers in the PCI memory and I O spaces respectively PCIBAR 2 and 3 are...

Page 26: ...sses Usually there is no conflict as ISA designs typically generate NOWS from the command strobe along with the address and the PCI 9052 command strobe assertion occurs after the first NOWS sampling f...

Page 27: ...or pin A11 Remove any jumper connecting CS3 JP2 13 to either CSROM JP2 14 or CSRAM JP2 10 The RDK default configuration maps CS3 to the ROM socket with CS3BASE programmed for a 1 MB range starting at...

Page 28: ...Customer Support at Address PLX Technology Inc 870 Maude Avenue Sunnyvale CA 94085 Phone 408 774 9060 800 759 3735 Fax 408 774 2169 Email USA http www plxtech com support Europe Middle East and South...

Page 29: ...pin socket SMT FAI FP1 8 2 Samtec TSM 108 01 T DV 8x2 header dual row SMT FAI JP1 JP2 9 1 Sullins Electronics EZC49DCMN S526 49X2 ISA connector 100 straddlemount SMT Sullins 760 744 0125 J6 10 6 Samte...

Page 30: ...pin half size Osc socket Thru hole Digi key U17 27 5 Harwin M20 9990305 3x1 header single row Thru hole Harwin JP3 JP7 28 1 Harting 9195107324 5x2 male connector IDC 10 Thru hole Harting J7 Manually i...

Page 31: ...mable Logic PG4 ISA Interface Connector PG4 128KB SRAM 32K x 32 PG4 001 18 04 2001 First Production 002 7 08 2002 Update RN20 RN21 RN22 from 10K to 1K on sheet 4 to reflect the BOM Update the BOM and...

Page 32: ...V VCC 3V3 VCC VCC VCC VCC 3V3 VCC T1 T45 T2 C23 10uF T3 C24 0 01uF T4 C91 10UF T5 C103 0 1uF T33 C92 10UF T6 T44 C5 0 047uF T7 C22 0 1uF T8 C14 0 01uF T9 C16 0 01uF T10 C17 0 01uF C93 10UF T11 C15 0 0...

Page 33: ...4 5 6 7 8 9 10 11 12 13 14 15 16 RN11 742 08 3 103 J XX 1 2 3 4 5 6 7 8 C37 0 1uF RN12 742 08 3 103 J XX 1 2 3 4 5 6 7 8 C49 0 01uF RN2 742 08 3 103 J XX 1 2 3 4 5 6 7 8 RN10 742 08 3 103 J XX 1 2 3 4...

Page 34: ...9 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 GND RESET_DRV 5V CHCHK S...

Page 35: ...BTERM 3 LINTi2 3 LW R 3 32MHZ 3 4 USER0 WAITo 3 4 LBE0 3 4 LCLK 3 4 LBE2 3 4 BCLKo 3 LHOLD 3 4 LBE3 3 4 TEST 3 WR 3 4 USER1 LLOCKo 3 4 RD 3 4 CHRDY 3 4 ALE 3 4 CS0 3 4 LRESET 3 4 USER2 CS2 3 4 ADS 3...

Page 36: ...PE57 PF41 PE3 PF16 PF89 PE56 PF81 PE5 PF15 PF100 PE52 PF85 PE1 PF13 PF96 PE49 PF83 FP2 84 Pin PLCC 9 8 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39...

Page 37: ...31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PG40 PG185...

Page 38: ...143 PH20 PH2 PH37 PH38 PH53 PH122 PH123 PH154 PH171 PH172 PH202 PH203 PH203 PH146 PH50 PH196 PH100 PH204 PH147 PH31 PH197 PH81 PH205 PH148 PH16 PH198 PH66 PH206 PH149 PH7 PH199 PH57 PH207 PH150 FP30 8...

Page 39: ...PI27 PI46 PI153 PI28 PI17 PI151 PI61 PI130 PI147 PI126 PI77 PI72 PI66 PI145 PI166 PI84 PI5 PI124 PI8 PI124 PI58 PI44 PI125 PI94 PI23 PI126 PI73 PI12 PI127 PI62 PI10 PI128 PI60 PI40 PI129 PI90 PI22 PI...

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