address was not a multiple of the range. The I/O region for the ISA device was from 0x308h to 0x317h.
To write to the first I/O location in the ISA card, care has to be taken. An access to location 0x0000fc08h
will map to location 0x308h on the local bus.
When accessing the I/O space, remember to use I/O read and write commands, not memory reads and
writes.
4.3
ISA NOWS# Delay Option
ISA protocol allows zero wait state operation for 16-bit memory only. At least one wait state is required for
16-bit I/O accesses and all 8-bit accesses. However, the PCI 9052 can support zero wait states for all
accesses.
ISA protocol uses the ISA card’s NOWS# output to reduce the number of wait states (from the default of
four wait states for 8-bit transfers or one wait state for 16-bit transfers). During 16-bit memory accesses,
the protocol specifies that the NOWS# output is sampled halfway through the first data valid time,
permitting zero wait state operation. During 16-bit I/O accesses, the protocol specifies that the NOWS#
output be ignored, thus 16-bit I/O cycles have one wait state. During 8-bit accesses, the protocol specifies
that the NOWS# output is sampled halfway through the
second
data valid time as well as halfway through
each subsequent data valid time, thus at least one wait state is inserted into each 8-bit access.
The PCI 9052 samples its NOWS# input halfway through the first data time and halfway through each
subsequent data time
for all accesses
. This allows all accesses to be truly “zero wait state” even though
ISA protocol allows zero wait state transfers for 16-bit memory accesses only. Sampling of NOWS#
during the first data time may cause conflict with ISA designs that expect the signal to be first sampled
during the second data time for all 8-bit accesses, or which expect NOWS# to be ignored during 16-bit I/O
accesses.
Usually there is no conflict, as ISA designs typically generate NOWS# from the command strobe along
with the address, and the PCI 9052 command strobe assertion occurs after the first NOWS# sampling for
16-bit I/O and all 8-bit accesses.
If there is a conflict, the CPLD can be used to delay the assertion of the PCI 9052 NOWS# input by one
clock cycle, ensuring that at least one wait state is inserted into all accesses, even formerly zero wait
state memory accesses.
The delay circuit is enabled by moving jumper JP7 from 1-2 to 2-3, as shown in Table 3-4 Configuration
Jumper Settings. Before configuring the NOWS# delay, determine whether the ISA card asserts the
NOWS# signal prior to the ISA command strobe (MEMRD#, MEMWR#, IORD# or IOWR) assertion. If it
does and it is an 8-bit card, or a 16-bit card which uses I/O accesses, then the NOWS# delay should be
enabled.
4.4
ISA Interface AEN Signal
The PCI 9052 floats the Local Address (LA) bus during reset, and drives the LA bus when it owns the
Local Bus and is idle. If during initialization a Local Bus device were to respond to an address on the idle
Local Bus, the device could subsequently assert an interrupt, which could hang the system since the
driver that knows how to clear the interrupt is not yet loaded.
Accordingly, ISA devices interfaced to the PCI 9052RDK-Lite ISA interface must not decode the ISA
address bus during initialization, nor do they need decode it between PCI 9052 transfers while the PCI
9052 owns the bus. However, many ISA cards decode the address bus whenever AEN is de-asserted (by
an ISA master). Since the PCI 9052RDK-Lite ISA interface does not support ISA masters, AEN is tied to
ground, and this does not disable AEN-gated address decoding during initialization, nor while the bus is
idle.
If the ISA card to be inserted into the PCI 9052RDK-Lite ISA connector relies solely on AEN toggling to
enable decoding of the address, the following solution can be applied.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
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© 2004 PLX Technology, Inc. All rights reserved.
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