background image

ROM
Socket

SRAM

CLOCK
CIRCUITS

ISA
INTERFACE

ROM power selection.
For 5V fit JP6 1-2
For 3V3 fit JP6 2-3

CS# Configuration. 
Fit links to choose
appropriate CS# for
SRAM and ROM

PLD
ISP header

PLD

NOWS# Operation
selection

91-0023-002-A

002

SRAM, FLASH, PLD and ISA

PLX TECHNOLOGY, INC.

870 Maude Ave,   Sunnyvale, CA 94085

Custom

4

9

Friday, July 12, 2002

www.plxtech.com

Title

Size

Document Number

Rev

Date:

Sheet

of

LA[27:2]

LA[27:2]

LD[31:0]

RD#

RCS0#

RD#

RCS1#

RWE#

RD#

RCS2#

RWE#

RD#

RCS3#

RWE#

TDI

TMS

RD#
WR#
LCLK

CSRAM#

CSROM#

IRQ4

IRQ3

IRQ5
IRQ6

IRQ15
IRQ2/9

IRQ14

XCSROM#

XCSRAM#

LA[27:2]

CHRDY

LD14

LD12

LA22

LA12

LD4

IRQ4

LA5

LA9

LA11

LD6

IRQ12

IRQ6

IRQ7

LA16

LA18

LD0

NOWSI#

LD13

LA18

LD10

CS0#

LA17

IRQ3

8MHZ

SMEMW#

LA2

LA4

LA6

LA13

LA14

LA17

LD2

LD11

LD8

CS1#

SMEMR#

-12V

LBE1#

LA10

IRQ11

LD15

LBE0#

LD7

LA23

IRQ5

LD3

LRESET/RESET_DRV

IRQ14

ALE

USER0/WAITo#

LA3

LA7

LD1

LA21

+12V

LD5

LA8

USER1/LLOCKo#

LA19

IRQ15

LD9

LA19

LA15

IRQ10

LA20

LBE3#

IRQ2/9

TDI

TDO

TDO

TMS

TCK

TCK

LD[31:0]

LD[31:0]

OSC

32MHZ

8MHZ

16MHZ

IRQ12

IRQ11

IRQ7
IRQ10

LBE3#

LBE2#

LBE1#

CS1#

LBE0#

CS0#

RWE#

IRQ2/9
IRQ3
IRQ4

IRQ6

IRQ15

IRQ14

IRQ12

IRQ11

IRQ10

IRQ5

IRQ7

RCS2#

RCS0#
RCS1#

ISA_INT

CSRAM#

SMEMR#
SMEMW#
RWE#

LA6

LA6

LA14

LA8

LD18

LA7

LD6

LD31

LA5

LD7

LD14

LD9

LD20

LA5

LA15

LD3

LD25

LD2

LD12

LA5

LBE1#

LD4

LA3

LA9

LA15

LD5

LD6

LD1

LD[31:0]

LA4

LA15

LA13

LA13

LA11

LA6

LA10

LD27

LA12

LA15

LD15

LD17

LA16

LA2
LA3

LA5

WR#

LA2

LA8

LA8

LD21

LA16

LA10

LA14

LD13

LA9

LA4

LA7

LA18

LA12

LD4

LD0

LA15

LA11

LA11

LD24

LA16

LA7

LA14

LD[31:0]

LA3

LD16

LD26

LA16

LA4

LA[27:2]

LA2

LA14

LD3

LD0

LA3

LA2

LA7

LBE0#

LA6

LA14

LA8

LD29

LA12

LA9

LA9

LD1

LA10

LA17

RD#

LA10

LA10

LD8

LD19

LD30

LA4

LA11

LA13

LA13

LD11

LA11

LA13

LD22

LD5

LD2

CSROMO#

LD[31:0]

LD7

LA2

LD10

LA12

LA12

LA4

LD23

LD28

LA5

LA6

LA9

LA[27:2]

LA[27:2]

LA3

LA7

LA16

LA8

LA20
LA21
LA22
LA23

ALE

CSROM#
CSROMO#
NOWSI#
NOWSO#
XCSRAM#
XCSROM#

RCS3#

NOWSI#

NOWSO#

LD[31:0]

3,5

LA[27:2]

3,5

LRESET

3,5

USER1/LLOCKo#

3,5

ALE

3,5

-12V

2

+12V

2

USER0/WAITo#

3,5

ISA_INT 3

8MHZ 3,5

16MHZ 3,5

32MHZ 3,5

LCLK

3,5

USER2/CS2#

3,5

USER3/CS3#

3,5

CS0#

3,5

CS1#

3,5

RD#

3,5

WR#

3,5

CHRDY

3,5

CHCHK#

3,5

LBE0#

3,5

LBE1#

3,5

LBE3#

3,5

LBE2#

3,5

XINT1 3
XINT2 3

NOWS#

3,5

LHOLDA

3,5

LHOLD

3,5

VCC

VCC

VCC

VCC

VCC

3V3

3V3

VCC

U10

SRAM 32KX8

10

9
8
7
6
5
4
3

25
24
21
23

2

26

1

20
22
27

11
12
13
15
16
17
18
19

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

CS
OE
WE

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

J6

ISA CONNECTOR FOOTPRINT

B1
B2
B3

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

B4
B5
B6
B7
B8
B9

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18

D1
D2
D3
D4
D5
D6
D7
D8
D9

D10
D11
D12
D13
D14
D15
D16
D17
D18

GND
RESET_DRV
+5V

CHCHK#

SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0

CHRDY

AEN

SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10

SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0

IRQ2/9
-5V
DRQ2
-12V
0WS
+12V
GND
SMEMW#
SMEMR#
IOW#
IOR#
DAK3#
DRQ3
DAK1#
DRQ1
RFSH#
BCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DAK2#
TC
BALE
+5V
OSC
GND

SBHE#

LA23
LA22
LA21
LA20
LA19
LA18
LA17

MEMR#

MEMW#

SD8
SD9

SD10
SD11
SD12
SD13
SD14
SD15

M16#
IO16#
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DAK0#
DRQ0
DAK5#
DRQ5
DAK6#
DRQ6
DAK7#
DRQ7
D16
MASTER#
GND

PC16

RN20

742-08-3-102-J-XX

1
2
3
4

5

6

7

8

PC13

PC5

U3

32MHz OSC

8

4

1

5

VCC

GND

NC

OUT

U17

14.3181MHz OSC

8

4

1

5

VCC

GND

NC

OUT

J7

IDC 10

1
2
3
4
5
6
7
8
9

10

R76

22R

1

2

C107

0.01uF

PC17

JP7

HEADER 3

1
2
3

PC8

FP1

32-pin PLCC

22
24
31

13
14
15
17
18
19
20
21

32

16

30

2

3

29

28

4

25

23

26

27

5

6

7

8

9

10

11

12

1

CE
OE
WE

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

VCC

GND

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

A18

R77
1K

L2

Ferrite 500mA

RN22

742-08-3-102-J-XX

1
2
3
4

5

6

7

8

PC1

RN23

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

PC9

PC18

PC7

R75
10K

RN21

742-08-3-102-J-XX

1
2
3
4

5

6

7

8

U5

EPM3064ATC100

38

86

11

26

33

43

53

59

39

91

6
8
9

10
12
13
14

16
17
19
20
21
23
25

29
30
31
32
35
36
37

54
56
57
58
60
61

63

52

64
67
68
69
71
75
76
79

81

80

83

85

92
93
94

97

96

98
99
100

40
41
42
44
45
46
47
48

62

4

73
15

87
89
88
90

3

18

34

51

66

82

84

65

74

78

95

GNDINT

GNDINT

GNDIO

GNDIO

GNDIO

GNDIO

GNDIO

GNDIO

VCCINT

VCCINT

I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O

I/O

I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O

I/O

I/O

I/O

I/O
I/O
I/O

I/O

I/O

I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O/TCK
I/O/TDI
I/O/TDO
I/O/TMS

I/GCLK1
I/GCLR
I/OE1
I/OE2/GCLK2

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

I/O

GNDIO

GNDIO

GNDIO

GNDIO

PC2

PC12

PC10

C98
0.1uF

U7

SRAM 32KX8

10

9
8
7
6
5
4
3

25
24
21
23

2

26

1

20
22
27

11
12
13
15
16
17
18
19

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

CS
OE
WE

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

R74
10K

PC19

PC6

U4

N.F.

14

7

1

8

VCC

GND

NC

OUT

PC14

C26
0.1uF

U15

SRAM 32KX8

10

9
8
7
6
5
4
3

25
24
21
23

2

26

1

20
22
27

11
12
13
15
16
17
18
19

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

CS
OE
WE

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

PC3

PC11

+

C27
10uF

C97

0.1uF

PC20

PC15

PC4

R78

22R

1

2

L1

Ferrite 500mA

R79
22R

1

2

PC21

JP2

HEADER 8X2

1
3
5
7
9
11
13
15

2
4
6
8

10
12
14
16

JP6

HEADER 3

1
2
3

U16

SRAM 32KX8

10

9
8
7
6
5
4
3

25
24
21
23

2

26

1

20
22
27

11
12
13
15
16
17
18
19

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

CS
OE
WE

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

Summary of Contents for PLX PCI 9052RDK-LITE

Page 1: ...PCI 9052RDK LITE Hardware Reference Manual...

Page 2: ......

Page 3: ...PCI 9052RDK LITE Hardware Reference Manual Version 1 3 October 2004 Website http www plxtech com Technical Support http www plxtech com support Phone 408 774 9060 800 759 3735 Fax 408 774 2169...

Page 4: ...to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX products PLX Technology and the PLX logo are registere...

Page 5: ...ocument describes the PLX PCI 9052RDK LITE a Rapid Development Kit from a hardware perspective It contains a description of all major functional circuit blocks on the board and also is a reference for...

Page 6: ......

Page 7: ...ON 15 4 1 1 Range Register 15 4 1 2 Base Address Re map Register 15 4 1 3 Chip Select Register 15 4 2 ISA REGISTER CONFIGURATION EXAMPLE 16 4 2 1 ISA Memory Mapping 16 4 2 2 ISA I O Mapping 16 4 2 3 C...

Page 8: ...ersion 12 LIST OF TABLES Table 3 1 PCI 9052RDK LITE Default Memory Map 6 Table 3 2 Serial EEPROM Contents 7 Table 3 3 PCI 9052RDK LITE Board Prototyping Area Footprints 11 Table 3 4 Configuration Jump...

Page 9: ...These allow designers to test simulate and debug their designs without fabricating their own boards saving considerable time and money in the development process and shortening time to market The RDK...

Page 10: ...l bus clock 5V to 3 3V voltage regulator Six logic analyzer headers with standard HP footprint to allow easy probing of local bus signals 25x25 0 1 through hole prototyping grid 1 2 RDK Installation T...

Page 11: ...I clock allowing the local bus to be run at an independent rate The buffered PCI bus clock output BCLKO may be connected to the local bus clock LCLK input through a 50 Ohm series resistor if desired P...

Page 12: ...fetch counter The local bus pre fetch counter can be programmed for 0 no pre fetch 4 8 16 or Continuous Pre fetch Mode pre fetch counter turned off The pre fetched data can be used as cached data if...

Page 13: ...PCI 9052 burst read write accesses to 128 Kbytes of SRAM provided in a 32 bit wide format An inexpensive 64 macrocell CPLD is used to generate various control signals for the RDK board While not requi...

Page 14: ...he preprogrammed data in the EEPROM is used to configure the RDK board during boot up The data includes device and functional information for plug and play PnP PCI memory resource allocation and initi...

Page 15: ...e 3 LAS3RR 31 16 FFF0 1Eh Local 0Ch LSW of Range for PCI to Local Address Space 3 LAS3RR 15 0 0000 1MB local address space for the RDK memory mapped ROM mapped into PCI memory space 20h Local 12h MSW...

Page 16: ...CS0BASE 15 0 0001 As a default this CS is not active as its pin is used as an ISA bus signal The local address range is set from 00000000 to 000FFFFFh to allow correct ISA Memory space accesses 50h L...

Page 17: ...are a few minor exceptions to ISA compatibility The PCI 9052RDK LITE board does not provide 5V to the ISA interface connector Also the PCI 9052 does not support ISA mastering nor ISA DMA operations L...

Page 18: ...interface the PCI 9052 to the ISA bus using a small CPLD makes the RDK as flexible as possible as a development platform It performs the following functions Clock division to generate 16 MHz and 8 MHz...

Page 19: ...8 15 16 54 pin TSOP 2 0 8mm pitch FP9 10 48 pin SSOP 2 300 wide 0 025 pitch FP23 24 20 pin SOIC wide 4 300 wide 0 05 pitch FP17 18 19 20 24 pin SSOP 2 150 wide 0 025 pitch FP21 22 44 pin TQFP 1 0 8mm...

Page 20: ...nd the Land Socket plugged into the Minigrid Socket These sockets are available from Ironwood Electronics web site www ironwoodelectronics com BGA Device Ironwood BGA Land Socket Ironwood Minigrid Soc...

Page 21: ...3 10 13 14 X X ROM Socket VCC Vcc 5 V Vcc 3 3 V JP6 1 2 2 3 NOWS Delay Disabled Enabled JP7 1 2 2 3 X Note 1 ISA Mode is selected by setting Jumper JP5 2 3 and programming INTCSR 12 1 in the EEPROM Th...

Page 22: ......

Page 23: ...address programmed into the LASxBA register must be a multiple of the appropriate range or 0 This restriction may require lowering the base address and increasing the range to ensure that both the IS...

Page 24: ...s to be set to cover the memory mapped region in Local Address Space 0 Based on the method described in section 4 1 3 the CS0BASE register value should be 0x00001201h Similarly the CS1BASE register ha...

Page 25: ...s a correctly programmed EEPROM is present 4 2 7 PCI Access to Local ISA Bus PCIBAR 0 and 1 are the addresses of the PCI 9052 registers in the PCI memory and I O spaces respectively PCIBAR 2 and 3 are...

Page 26: ...sses Usually there is no conflict as ISA designs typically generate NOWS from the command strobe along with the address and the PCI 9052 command strobe assertion occurs after the first NOWS sampling f...

Page 27: ...or pin A11 Remove any jumper connecting CS3 JP2 13 to either CSROM JP2 14 or CSRAM JP2 10 The RDK default configuration maps CS3 to the ROM socket with CS3BASE programmed for a 1 MB range starting at...

Page 28: ...Customer Support at Address PLX Technology Inc 870 Maude Avenue Sunnyvale CA 94085 Phone 408 774 9060 800 759 3735 Fax 408 774 2169 Email USA http www plxtech com support Europe Middle East and South...

Page 29: ...pin socket SMT FAI FP1 8 2 Samtec TSM 108 01 T DV 8x2 header dual row SMT FAI JP1 JP2 9 1 Sullins Electronics EZC49DCMN S526 49X2 ISA connector 100 straddlemount SMT Sullins 760 744 0125 J6 10 6 Samte...

Page 30: ...pin half size Osc socket Thru hole Digi key U17 27 5 Harwin M20 9990305 3x1 header single row Thru hole Harwin JP3 JP7 28 1 Harting 9195107324 5x2 male connector IDC 10 Thru hole Harting J7 Manually i...

Page 31: ...mable Logic PG4 ISA Interface Connector PG4 128KB SRAM 32K x 32 PG4 001 18 04 2001 First Production 002 7 08 2002 Update RN20 RN21 RN22 from 10K to 1K on sheet 4 to reflect the BOM Update the BOM and...

Page 32: ...V VCC 3V3 VCC VCC VCC VCC 3V3 VCC T1 T45 T2 C23 10uF T3 C24 0 01uF T4 C91 10UF T5 C103 0 1uF T33 C92 10UF T6 T44 C5 0 047uF T7 C22 0 1uF T8 C14 0 01uF T9 C16 0 01uF T10 C17 0 01uF C93 10UF T11 C15 0 0...

Page 33: ...4 5 6 7 8 9 10 11 12 13 14 15 16 RN11 742 08 3 103 J XX 1 2 3 4 5 6 7 8 C37 0 1uF RN12 742 08 3 103 J XX 1 2 3 4 5 6 7 8 C49 0 01uF RN2 742 08 3 103 J XX 1 2 3 4 5 6 7 8 RN10 742 08 3 103 J XX 1 2 3 4...

Page 34: ...9 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 GND RESET_DRV 5V CHCHK S...

Page 35: ...BTERM 3 LINTi2 3 LW R 3 32MHZ 3 4 USER0 WAITo 3 4 LBE0 3 4 LCLK 3 4 LBE2 3 4 BCLKo 3 LHOLD 3 4 LBE3 3 4 TEST 3 WR 3 4 USER1 LLOCKo 3 4 RD 3 4 CHRDY 3 4 ALE 3 4 CS0 3 4 LRESET 3 4 USER2 CS2 3 4 ADS 3...

Page 36: ...PE57 PF41 PE3 PF16 PF89 PE56 PF81 PE5 PF15 PF100 PE52 PF85 PE1 PF13 PF96 PE49 PF83 FP2 84 Pin PLCC 9 8 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39...

Page 37: ...31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PG40 PG185...

Page 38: ...143 PH20 PH2 PH37 PH38 PH53 PH122 PH123 PH154 PH171 PH172 PH202 PH203 PH203 PH146 PH50 PH196 PH100 PH204 PH147 PH31 PH197 PH81 PH205 PH148 PH16 PH198 PH66 PH206 PH149 PH7 PH199 PH57 PH207 PH150 FP30 8...

Page 39: ...PI27 PI46 PI153 PI28 PI17 PI151 PI61 PI130 PI147 PI126 PI77 PI72 PI66 PI145 PI166 PI84 PI5 PI124 PI8 PI124 PI58 PI44 PI125 PI94 PI23 PI126 PI73 PI12 PI127 PI62 PI10 PI128 PI60 PI40 PI129 PI90 PI22 PI...

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