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APPENDIX B
Table B-5-6a Terminal descriptions of RSI-PPVC-AXRY-ENPG-PG2 and RSI-PPVC-AXRY-ENPG-PG8
B.5.6 Extension Differential PG Card with Frequency Dividing
(RSI-PPVC-AXRY-ENPG-PG2 and RSI-PPVC-AXRY-ENPG-PG8)
Terminal
Pin
Definition
Function Description
Terminal Arrangement
J3
1
A+
Encoder signal A positive
1
2
3
4
5
6
7
8
9
A+
A-
NC
+5V
B+
COM
B-
Z-
Z+
2
A-
Encoder signal A negative
3
B+
Encoder signal B positive
4
B-
Encoder signal B negative
5
Z+
Encoder signal Z positive
6
Null
Vacant internally
7
+5V
Encoder 5V power supply positive
8
COM
Encoder power supply negative
9
Z-
Encoder signal Z negative
J7, J8
OA+
Frequency dividing output signal A positive
OA
-
OB
+
OB
-
OZ
+
OZ
-COM
OA
+
PE
OA-
Frequency dividing output signal A negative
OB+
Frequency dividing output signal B positive
OB-
Frequency dividing output signal B negative
OZ+
Frequency dividing output signal Z positive
OZ-
Frequency dividing output signal Z negative
COM
Signal power ground
PE
Shield connecting point
CN1
18-pin FFC interface, connecting to J4 on the control board of the AC drive
Table B-5-6b Descriptions of DIP Switch of RSI-PPVC-AXRY-ENPG-PG8
Figure B-5-6 Port circuit of RSI-PPVC-AXRY-ENPG-PG2 and RSI-PPVC-AXRY-ENPG-PG8
Shield
26C31
26C32
5V
COM
A+,B+,Z+
A-,B-,Z-
COM
Frequency
dividing output
PG card
VCC
0V
A+,B+,Z+
A-,B-,Z-
A+,B+,Z+
A-,B-,Z-
PE
Twisted
pair
Encoder
Address Setting
Frequency Dividing Coefficient
DIP Switch
1 2 3 4 5
Value
0 0 0 0 0
0
No output
ON
1
2
3
4
5
Frequency dividing
coefficient setting
S1
0 0 0 0 1
1
No output
0 0 0 1 0
2
Frequency divided by 4
0 0 0 1 1
3
Frequency divided by 6
1 1 1 1 1
31
Frequency divided by 62
