Layout Information
2-2
TSEV83102G0B - Evaluation Board User Guide
2166B–BDC–04/03
2.4
Power Supplies
The bottom metal layers 5 and 7 and 11 are dedicated to power supply traces (V
EE
,
DV
EE
, V
EET
, V
DD
, V
PLUSD
and V
CC
).
The supply traces are approximately 6 mm wide in order to present low impedance, and
are surrounded by a ground plane connected to the two inner ground planes.
The analog and digital negative power supply traces are independent, but the possibility
exists to short-circuit both supplies on the top metal layer).
No difference in ADC high speed performance is observed when connecting both nega-
tive supply planes together. Obviously one single negative supply plane could be used
for the circuit.
Each power supply incoming is bypassed by a 1 µF Tantalum capacitor in parallel with
1 nF chip capacitor.
Each power supply access is decoupled very close to the device by 10 nF and 100 pF
surface mount chip capacitors in parallel.
Note:
The decoupling capacitors are superposed. In this configuration, the 100 pF capacitors
must be mounted first.
