Atmel TSEV83102G0B User Manual Download Page 5

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Overview

1-2

TSEV83102G0B - Evaluation Board User Guide

2166B–BDC–04/03

1.2

TSEV83102G0B
Evaluation Board

Figure 1-1. TSEV83102G0B Block Diagram

CLK

CLKB

Differential

Clock inputs

Z0 = 50

Ω

Z0 = 50

Ω

CLK

CLKB

TS83102G0B

VIN

VINB

Differential

analog inputs

Z0 = 50

Ω

Z0 = 50

Ω

VIN

VINB

GAIN

SDA

SDAEN

VEE

TEST

VEE

B/BG

PGEB

DR/DRB

D0/D0B

Z0 = 50

Ω

Z0 = 50

Ω

Z0 = 50

Ω

Z0 = 50

Ω

D7/D7B

PC/PCB

VCC

DRRB

VCC = +5V

GND

VPLUSD

GND = 0V

VPLUSD = -0.8V (ECL)
VPLUSD = 1.6V (LVDS)

VEE

DVEE

DIODE

VEE = -5V

DVEE = -5V

J - diode

V - diode

DRRB

V-GND

I-GND

CAL1

CAL2

L = 50 mm typ
LVIN/VINb = LCLK/CLKb = 43 mm typ
Loutputs = 58 mm typ

+5V

VCC

+5V

VEE

GND

+5V

DVEE

Short-circuit
possibility
here

Summary of Contents for TSEV83102G0B

Page 1: ...ADC 10 bit 2 Gsps Evaluation Board TSEV83102G0B User Guide...

Page 2: ...4 Power Supplies 2 2 Section 3 Operating Procedures and Characteristics 3 1 3 1 Introduction 3 1 3 2 Operating Procedure ECL Mode 3 1 3 3 Use with DMUX Evaluation Board 3 2 3 4 Electrical Characteris...

Page 3: ...iption 5 1 5 1 TS83102G0B Pinout 5 1 5 2 Thermal Characteristics 5 3 5 2 1 Thermal Resistance from Junction to Ambient Rthja 5 3 5 2 2 Thermal Resistance from Junction to Case Rthjc 5 4 5 2 3 Heatsink...

Page 4: ...rature range The TS83102G0B Evaluation Board EB is very straightforward as it only implements the TS83102G0B ADC device SMA connectors for input output accesses and a 2 54 mm pitch connector compatibl...

Page 5: ...VINB Differential analog inputs Z0 50 Z0 50 VIN VINB GAIN GA SDA SDA OA SDAEN VEE TEST VEE B BG PGEB DR DRB D0 D0B Z0 50 Z0 50 Z0 50 Z0 50 D7 D7B PC PCB VCC DRRB VCC 5V GND VPLUSD GND 0V VPLUSD 0 8V...

Page 6: ...4003 dielectric layer characteristics are very close to PTFE in terms of insertion loss characteristics A BT Epoxy dielectric layer of 0 9 mm total thickness which is sandwiched between the upper grou...

Page 7: ...mbedding fixture are provided by SMA connectors Reference VITELEC 142 0701 851 Connector mounting plates have been used for fastening the SMA connectors 1 5 Digital Outputs Accesses Access to the diff...

Page 8: ...supplies 2 2 AC Inputs Digital Outputs The board uses 50 impedance microstrip lines for the differential analog inputs clock inputs and differential digital outputs The input signals and clock signals...

Page 9: ...re independent but the possibility exists to short circuit both supplies on the top metal layer No difference in ADC high speed performance is observed when connecting both nega tive supply planes tog...

Page 10: ...d the TS83102G0B clock inputs with bal anced signals Directly connect the RF sources to the in phase analog and clock inputs of the converter However dynamic performances can be somewhat improved by e...

Page 11: ...th the TSEV83102G0B ADC evaluation board The DEMUX input configuration has been optimized to be connected to the TS83102G0B ADC CBGA152 package When using the DEMUX board with the ADC board do not for...

Page 12: ...5 5 V Digital negative supply voltage DVEE GND to 5 5 V Digital positive supply voltage VPLUSD GND 1 1 to 2 0 V Negative supply voltage VEE GND to 5 5 V Maximum difference between negative supply vol...

Page 13: ...pply current dedicated to TS83102G0B ADC only ICC 144 205 mA IPLUSD 164 mA IEEA 514 630 mA IEED 170 180 mA Positive supply voltage not used by default installed dedicated to MC100EL16 differential rec...

Page 14: ...in phase clock input amplitude is 1V peak to peak centered on 0V Ground or 1 3V ECL on common mode As for the analog input either clock input can be chosen if the single ended output mode is used leav...

Page 15: ...to 1 15 The gain adjust transfer function is given below Figure 4 1 ADC Gain Adjust 4 6 SMA Connectors and Microstrip Lines De embedding Fixture Attenuation in microstrip lines can be found by taking...

Page 16: ...ut in this particular case it is necessary to have exactly 2 diodes in the A10 to ground direction of conduction Figure 4 2 Recommended Die Junction Temperature Monitoring Function Implemen tation Tes...

Page 17: ...nts This modification in Revision B devices implies the modification of the processing of the VDIODE characteristic if any but above all it allows the user to implement a digital temper ature sensor t...

Page 18: ...by 32 thus allowing for a quick debug phase of the ADC at maximum speed rate When active this fuction makes the ADC output only 1 out of 32 data thus resulting in a data rate which is 32 times slower...

Page 19: ...ing of the Data Ready output signal 4 11 Sampling Delay Adjusting One delay adjust controlled by SDA potentiometer is available in order to add a delay to the input clock of the ADC This allows the us...

Page 20: ...Clock Input Configuration RF Generator RF Generator 121 dBc Hz at 1 KHz offset from fc 0 180 Hybrid 0 180 Hybrid BPF Data Acquisition System TS83102G0B ADC 117 dBc Hz at 20 KHz offset from fc PC GPIB...

Page 21: ...PLUSD VEE VPLUSD GND VEE VEE VEE GND PGEB VEE VEE VCC VEE VCC VCC GND VCC GND GND VCC GND VCC GND GND GND VEEH VCCTH VCCTH GND GND VEE GND VEE TS83102G0B CBGA152 cavity down GND GND GND VEEH VEEH VCCT...

Page 22: ...phase analog input signal of the differential sample and hold preamplifier VINB R6 Inverted phase analog input signal of the differential sample and hold preamplifier Clock Inputs CLK E1 In phase clo...

Page 23: ...rn generator enable Digitized input delivered at outputs according to B GB if PGEB is floating or connected to GND Checkerboard pattern delivered at outputs if PGEB is driven with ECL low level or con...

Page 24: ...power dissipa tion 4 7W A method should be chosen for cooling that allows less than 4 0 C W for the case to ambient thermal resistance Rthca The thermal resistance of the board is a high value within...

Page 25: ...ng Level Comments JTSX83102G0 1V1B Die Ambient Prototype ON REQUEST ONLY Please contact Marketing TSX83102G0BGL CBGA 152 Ambient Prototype Prototype Version TS83102G0BCGL CBGA 152 C grade 0 C TC TJ 90...

Page 26: ...EV83102G0B Evaluation Board User Guide 6 1 Rev 2166B BDC 04 03 Section 6 Schematics 6 1 TSEV83102G0B Electrical Schematic Figure 6 1 through Figure 6 7 show the electrical schematic of the TSEV83102G0...

Page 27: ...Schematics 6 2 TSEV83102G0B Evaluation Board User Guide 2166B BDC 04 03 Figure 6 1 TSEV83102G0B Electrical Schematic...

Page 28: ...e Description Figure 6 3 Metal Layer 2 and 4 Ground Planes Figure 6 4 Metal Layer 3 and 3 bis Power Supplies and Ground Planes Figure 6 5 Metal Layer 5 Solder Side Figure 6 6 TSEV83102G0B Evaluation B...

Page 29: ...ong Kong Tel 852 2721 9778 Fax 852 2722 1369 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Memory 2325 Orchard Parkway San Jose CA 9...

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