TSEV83102G0B - Evaluation Board User Guide
2-1
Rev. 2166B–BDC–04/03
Section 2
Layout Information
2.1
Board
The TS83102G0B requires proper board layout for optimum full speed operation.
The following explains the board layout recommendations and demonstrates how the
Evaluation Board fulfills these implementation constraints.
A single low impedance ground plane is recommended, since it allows the user to lay
out signal traces and power planes without interrupting the ground plane.
Therefore a multi-layer board structure has been retained for the TSEV83102G0B.
Six copper metal layers are used, dedicated respectively (from top to bottom) to the sig-
nal traces, ground planes and power supplies.
2.2
AC Inputs/Digital
Outputs
The board uses 50
Ω
impedance microstrip lines for the differential analog inputs, clock
inputs, and differential digital outputs.
The input signals and clock signals must be routed on one layer only, without using any
through-hole vias. The line lengths are matched to within 2 mm.
The digital output lines are 50
Ω
differentially terminated.
The output data trace lengths are matched to within 0.25 inch (6 mm) to minimize the
data output delay skew.
For the TSEV83102G0B the propagation delay is approximately 6.1 ps/mm
(155 ps/inch). The RO4003 typical dielectric constant is 3.4 at 10 GHz.
For more informations about different output termination options refer to the specifica-
tion application notes.
2.3
DC Function
Settings
The DC signal traces are low impedance.
They have been routed with a 50
Ω
impedance near the device because of space
restriction.
