![Atmel TSEV83102G0B User Manual Download Page 13](http://html1.mh-extra.com/html/atmel/tsev83102g0b/tsev83102g0b_user-manual_3003514013.webp)
Operating Procedures and Characteristics
3-4
TSEV83102G0B - Evaluation Board User Guide
2166B–BDC–04/03
3.5
Operating
Characteristics
The power supplies denoted by V
CC
, V
EE
, DV
EE
and V
PLUSD
are dedicated to the
TS83102G0B ADC.
The power supplies denoted V
EET
, V
DD
are dedicated to the optional MC100EL16 asyn-
chronous differential receivers.
Table 3-2. Electrical Operating Characteristics
Parameter
Symbol
Value
Unit
Min
Typ
Max
Positive supply voltage
(dedicated to TS83102G0B ADC only)
V
CC
4.75
5
5.25
V
V
PLUSD
–
ECL: -0.8
LVDS: 1.6
–
V
V
V
EEA
-5.25
-5
-4.75
V
V
EED
-5.25
-5
-4.75
V
Positive supply current
(dedicated to TS83102G0B ADC only)
I
CC
–
144
205
mA
I
PLUSD
–
164
–
mA
I
EEA
–
514
630
mA
I
EED
–
170
180
mA
Positive supply voltage not used by default – installed
(dedicated to MC100EL16 differential receivers)
V
EET
-5.25
-5
-4.75
V
V
DD
-2.15
-2
-185
V
Positive supply current not used by default – installed
(dedicated to MC100EL16 differential receivers)
I
EET
–
180
–
mA
I
DD
–
480
–
mA
Nominal power dissipation (without receivers)
PD
–
4.6
5.1
(T
J
= 125
°
C)
W
Analog input impedance
Z
IN
–
50
–
Ω
Full power analog input bandwidth (-3 dB)
–
–
3.0
–
GHz
Analog input voltage range (differential mode)
V
IN
-125
–
125
mV
Clock input impedance
–
–
50
–
Ω
Clock input voltage compatibility (single-ended or
differential) (See Application Notes)
–
ECL levels or 4 dBm (typ) into 50
Ω
–
Clock input power level into 50
Ω
termination resistor
–
-2
2
4
dBm