Application Information
TSEV83102G0B - Evaluation Board User Guide
4-7
2166B–BDC–04/03
4.12
Test Bench
Description
Figure 4-8. Differential Analog and Clock Input Configuration
Figure 4-9. Single-ended Analog and Clock Input Configuration
RF Generator
RF Generator
-121 dBc/Hz at 1 KHz
offset from fc
0
−
180
°
Hybrid
0
−
180
°
Hybrid
BPF
Data Acquisition
System
TS83102G0B
ADC
-117 dBc/Hz at 20 KHz
offset from fc
PC
GPIB
CLKB
CLK
DR
10 Data
Tunable delay line
VINB
VIN
Synchro 10 MHz
BPF
Data Acquisition
System
TS83102G0B
ADC
PC
GPIB
(50
Ω
) CLKB
CLK
DR
10 Data
Tunable delay line
VINB (50
Ω
)
VIN
Synchro 10 MHz
RF Generator
RF Generator
