Application Information
4-6
TSEV83102G0B - Evaluation Board User Guide
2166B–BDC–04/03
4.10
Data Ready
Output Signal
Reset
A sub-screw connector is provided for the DRRB command.
The Data Ready signal is reset on the falling edge of the DRRB input command, on ECL
logical low level (-1.8V). DRRB may also be tied to V
EE
= -5V for Data Ready output sig-
nal master reset. As long as DRRB remains at a logical low level, (or tied to V
EE
= -5V),
the Data Ready output remains at logical zero and is independent of the external free
running encoding clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps
typically.
TRDR is measured between the -1.3V point of the falling edge of the DRRB input com-
mand and the zero crossing point of the differential Data Ready output signal (DR,
DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
The Data Ready output signal restarts on the DRRB command rising edge, ECL logical
high levels (-0.8V).
DRRB may also be grounded, or is allowed to float, for normal free running of the Data
Ready output signal.
4.11
Sampling Delay
Adjusting
One delay adjust, controlled by SDA potentiometer, is available in order to add a delay
to the input clock of the ADC. This allows the user to tune the instant of the internal sam-
pling. To enable this delay adjustment there is an SDAEN pin on the chip. In the current
revision, the SDAEN function corresponds to the OA labels (OA jumper and OA
potentiometer).
The OA potentiometer has been removed and short-circuited to V
EE
.
Use the jumper denoted OA to enable the sampling delay adjustment:
If OA is left floating or tied to GND, the SDA is disabled
If OA is tied to V
EE
, the SDA is enabled
The SDA input varies from -0.5 to 0.5V, according to the SDA potentiometer position.
The variation of the delay around its nominal value as a function of the SDA voltage is
more or less linear, as shown in Figure 4-7 (simulation results).
Figure 4-7. Sampling Delay Adjust
Note:
The variation of the delay as a function of temperature is insignificant.
400p
300p
200p
100p
-500m
-400m
-300m
-200m
-100m
100m
SDAVAL
Delay
200m
300m
400m
500m
0m
Delay in the variable delay cell at 60
°
C
: (cross(clip((VT("delop") - VT("delon")) 4e-10 2e-09) 0 2 "rising") - cross(clip((VT("delip") - VT("delin")) 2.5e-10 2e-09) 0 2 "rising")) (60
°
C)
